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45 条记录 (耗时 0.019 秒)

    Clock ride-over method and circuit
    1.
    发明授权
    Clock ride-over method and circuit 失效
    时钟转换方法和电路

    公开(公告)号：US06907095B1

    公开(公告)日：2005-06-14

    申请号：US09709203

    申请日：2000-11-09

    申请人： Fumio Nakano ,  Hitoshi Fujita

    发明人： Fumio Nakano ,  Hitoshi Fujita

    IPC分类号： H03K21/38 ,  H04L7/00 ,  H04L7/04

    CPC分类号： H04L7/0012

    摘要： A clock ride-over circuit in which clock ride-over may be achieved even if jitter is contained in clocks prior to and subsequent to ride-over and no control input signal for write and readout is applied from outside. A clock prior to rideover CLK—1 is detected by a clock subsequent to ride-over CLK—2 which is of a higher speed than the clock prior to ride-over. A timing signal TIM of a constant period, generated by a counter adapted for self-running with the clock prior to ride-over, is compared to the phase comparison signal COMP which is the result of the clock detection. Stable clock ride-over is possible by the phase comparison signal COMP having a pulse width larger than the jitter period of the clock subsequent to ride-over.

    摘要翻译： 即使在骑乘之前和之后的时钟中包含抖动也可以实现时钟转换的时钟转换电路，并且不从外部施加用于写入和读出的控制输入信号。 Rideover之前的一个时钟CLK乘以一个比乘法之前的时钟更快的乘法器CLK-2之后的时钟来检测。 由适应于在乘坐之前的时钟自行运行的计数器产生的恒定周期的定时信号TIM与作为时钟检测结果的相位比较信号COMP进行比较。 可以通过相位比较信号COMP具有比乘坐后的时钟的抖动周期大的脉冲宽度的稳定的时钟跳变。

    Delay circuit and voltage controlled oscillation circuit
    2.
    发明授权
    Delay circuit and voltage controlled oscillation circuit 失效
    延迟电路和压控振荡电路

    公开(公告)号：US08362844B2

    公开(公告)日：2013-01-29

    申请号：US12974782

    申请日：2010-12-21

    申请人： Fumio Nakano

    发明人： Fumio Nakano

    IPC分类号： H03K3/03

    CPC分类号： H03L7/0995 ,  H03K2005/00039 ,  H03K2005/00202 ,  H03K2005/00208

    摘要： A delay circuit includes a delay unit having a first and a second power supply terminals, a pair of differential signal input terminals and a pair of differential signal output terminals. The signals entered to the pair of differential signal input terminals are delayed and output at the pair of differential signal output terminals. The delay circuit also includes a current controller that exercises control to cause a current of a current source, controlled by a current control terminal, to flow through the first and second power supply terminals of the delay unit. The delay circuit also includes a voltage controller that exercises control to provide for a constant potential difference between the first and the second power supply terminals (FIG. 1).

    摘要翻译： 延迟电路包括具有第一和第二电源端子的延迟单元，一对差分信号输入端子和一对差分信号输出端子。 输入到该对差分信号输入端子的信号在差动信号输出端子对被延迟输出。 延迟电路还包括电流控制器，其进行控制以使由电流控制端子控制的电流源的电流流过延迟单元的第一和第二电源端子。 延迟电路还包括电压控制器，其进行控制以在第一和第二电源端子之间提供恒定的电位差（图1）。

    Magnetic recording apparatus comprising a magnetic recording medium and a magnetic head each coated with a coating of a binder and a specified fluorolubricant
    3.
    发明授权
    Magnetic recording apparatus comprising a magnetic recording medium and a magnetic head each coated with a coating of a binder and a specified fluorolubricant 失效
    磁记录装置包括磁记录介质和磁头，各自涂覆有粘合剂和特定氟润滑剂的涂层

    公开(公告)号：US5219651A

    公开(公告)日：1993-06-15

    申请号：US790084

    申请日：1991-11-13

    申请人： Mitsuyosi Shoji ,  Takayuki Nakakawaji ,  Yutaka Ito ,  Shigeki Komatsuzaki ,  Fumio Nakano

    发明人： Mitsuyosi Shoji ,  Takayuki Nakakawaji ,  Yutaka Ito ,  Shigeki Komatsuzaki ,  Fumio Nakano

    IPC分类号： G11B5/00 ,  G11B5/40 ,  G11B5/725

    CPC分类号： G11B5/00 ,  G11B5/40 ,  G11B5/725 ,  Y10S428/90 ,  Y10T428/25 ,  Y10T428/265

    摘要： A magnetic recording medium which comprises a non-magnetic substrate, a thin film magnetic layer formed on the surface of the substrate and an organic thin film protective layer formed on the magnetic layer, the organic thin film protective layer having a thickness of not more than 100 nm and containing a filler having a particle size of not more than 50 nm, wherein the surface of the organic thin film protective layer is further coated with a fluorine-based compound represented by the following general formula:F(C.sub.3 F.sub.6 --I--).sub.x --C.sub.2 F.sub.4 --,F(C.sub.3 F.sub.6 --O--).sub.x --(CF.sub.2 O).sub.y --(CF.sub.2).sub.z --or--(C.sub.2 F.sub.4 --O--).sub.y --(CF.sub.2 --CF.sub.2 --, wherein x, y and z are integers of 1 or more, and a magnetic head whose surface is coated with a lubricant thin film having the same composition as that of the above organic thin film protective layer have an excellent sliding durability, and a magnetic recording apparatus using these magnetic recording medium and magnetic head has a high reliability.

    摘要翻译： 一种磁记录介质，其包括非磁性基板，形成在所述基板的表面上的薄膜磁性层和形成在所述磁性层上的有机薄膜保护层，所述有机薄膜保护层的厚度不大于 100nm，并且含有粒径不大于50nm的填料，其中有机薄膜保护层的表面进一步涂覆有由以下通式表示的氟基化合物：F（C 3 F 6 -I） x-C2F4-，F（C3F6-O-）x-（CF2O）y-（CF2）z-或 - （C2F4-O-）y-（CF2-CF2-，其中x，y和z是1 以上的表面被涂覆有与上述有机薄膜保护层相同组成的润滑剂薄膜的磁头具有优异的滑动耐久性，并且使用这些磁记录介质和磁头的磁记录装置具有 高可靠性。

    Crystalline cephalosporin compounds
    4.
    发明授权
    Crystalline cephalosporin compounds 失效
    结晶头孢菌素化合物

    公开(公告)号：US4959469A

    公开(公告)日：1990-09-25

    申请号：US315917

    申请日：1989-02-27

    申请人： Susumu Nakagawa ,  Ryosuke Ushijima ,  Fumio Nakano ,  Koji Yamada ,  Eiichi Mano

    发明人： Susumu Nakagawa ,  Ryosuke Ushijima ,  Fumio Nakano ,  Koji Yamada ,  Eiichi Mano

    IPC分类号： A61K31/545 ,  C07D501/46

    CPC分类号： C07D501/46 ,  A61K31/545 ,  C07D501/18 ,  C07D501/38

    摘要： The present invention relates to stable cyrstalline (6R,7R)-7-[(Z)-2-(2-aminothiazol-4-yl)-2-(1-carboxy-1-methylethoxyimino)acetamido]-3-(5,6-dihydroxy-2-methyl-2-isoindolinium)-3-cephem-4-carboxylate sulfate or its hydrate, a process for production of the compound and (6R,7R)-7-[(Z)-2-(2-aminothiazol-4-yl)-2-(1-carboxyl-1-methylethoxyimino)acetamido]-3-(5,6-dihydroxy-2-methyl-2-isoindolinium)methyl-3-cephem-4-carboxylate hydrochloride or its hydrate which is a starting material useful for the production of the desired compound of the present invention.

    摘要翻译： 本发明涉及稳定的cyrstalline（6R，7R）-7 - [（Z）-2-（2-氨基噻唑-4-基）-2-（1-羧基-1-甲基乙氧基亚氨基）乙酰氨基] -3-（ 5,6-二羟基-2-甲基-2-异二氢吲哚鎓）-3-头孢烯-4-羧酸甲酯硫酸盐或其水合物，该化合物的制备方法和（6R，7R）-7 - [（Z）-2 - （2-氨基噻唑-4-基）-2-（1-羧基-1-甲基乙氧基亚胺）乙酰胺基] -3-（5,6-二羟基-2-甲基-2-异二氢吲哚鎓）甲基-3-环丙基 - 4-羧酸盐酸盐或其水合物，其为可用于制备本发明所需化合物的原料。

    Pleochroic color display device
    6.
    发明授权
    Pleochroic color display device 失效
    多色彩色显示设备

    公开(公告)号：US4396251A

    公开(公告)日：1983-08-02

    申请号：US125478

    申请日：1980-02-28

    申请人： Akio Mukoh ,  Fumio Nakano ,  Hideaki Kawakami ,  Hirosada Morishita ,  Mikio Sato ,  Hidetoshi Abe ,  Shuji Imazeki

    发明人： Akio Mukoh ,  Fumio Nakano ,  Hideaki Kawakami ,  Hirosada Morishita ,  Mikio Sato ,  Hidetoshi Abe ,  Shuji Imazeki

    IPC分类号： G09F9/00 ,  G02F1/1335 ,  G02F1/137 ,  G09F9/30 ,  G09F9/35 ,  G02F1/13

    CPC分类号： G02F1/13737 ,  G02F1/133514

    摘要： A pleochroic color display device is provided which comprises a layer of guest-host type liquid crystal sandwiched between two transparent electrodes for driving the liquid crystal, the guest-host liquid crystal containing a dichroic dye as guest material, and a color filter disposed in front or rear of the layer of the guest-host type liquid crystal. High contrast pleochroic color displays can be obtained by selecting a blackish dye as the dichroic dye. Dichroic displays other than white ones can be produced by the use of a single liquid crystal cell and a single color filter (with one color).

    摘要翻译： 提供了一种双色彩色显示装置，其包括夹在用于驱动液晶的两个透明电极之间的客体主体型液晶层，包含作为客体材料的二色性染料的客体主体液晶和设置在前面的滤色器 或客体主体型液晶层的后方。 通过选择黑色染料作为二色性染料，可以获得高对比度多色显色。 可以通过使用单个液晶单元和单个滤色器（一种颜色）来产生除白色以外的二向色显示。

    Buffer circuit
    8.
    发明授权
    Buffer circuit 有权
    缓冲电路

    公开(公告)号：US06703864B2

    公开(公告)日：2004-03-09

    申请号：US09728103

    申请日：2000-12-01

    申请人： Junichi Takeuchi ,  Fumio Nakano

    发明人： Junichi Takeuchi ,  Fumio Nakano

    IPC分类号： H03K19094

    CPC分类号： H03K19/018528

    摘要： An output buffer circuit of a Pseudo Emitter Coupled Logic (PECL) uses a common level which is generated by a resistance division so that the common level is unstable to follow to a gradient of power source variation and an output signal level of the output buffer circuit is apt to be off from a level of the PECL. An output buffer circuit of PECL according to the present invention comprises: a first output terminal; a second output terminal; a first resistor connected between the first output terminal and a output terminal of a common level generator; a second resister connected between the second output terminal and the output terminal of the common level generator; and a driver circuit which makes a current from the first output terminal to the second output terminal through the first resistor and second resistor when a first input signal and a second input signal complementary to the first input signal result a first data, and makes a current from the second output terminal to the first output terminal through the second resistor and the first resistor when the first input signal and the second input signal result a second data; a common level which follows its fluctuation to that of power source is supplied to the connecting point of the first and second resistors.

    摘要翻译： 伪发射极耦合逻辑（PECL）的输出缓冲电路使用由电阻分割产生的公共电平，使得公共电平不稳定以跟随电源变化的梯度和输出缓冲电路的输出信号电平 容易脱离PECL的水平。 根据本发明的PECL的输出缓冲电路包括：第一输出端; 第二输出端子; 连接在所述第一输出端子和公共电平发生器的输出端子之间的第一电阻器; 连接在第二输出端子和公共电平发生器的输出端子之间的第二电阻器; 以及驱动电路，当与所述第一输入信号互补的第一输入信号和第二输入信号产生第一数据时，通过所述第一电阻器和所述第二电阻器将从所述第一输出端子流到所述第二输出端子的电流产生电流 当第一输入信号和第二输入信号产生第二数据时，通过第二电阻器和第一电阻器从第二输出端子到第一输出端子; 将其波动与电源的波动的共同电平提供给第一和第二电阻器的连接点。