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    System and method for device-to-device synchronization
    1.
    发明授权
    System and method for device-to-device synchronization 有权

    公开(公告)号：US11330542B2

    公开(公告)日：2022-05-10

    申请号：US16716140

    申请日：2019-12-16

    Applicant: Futurewei Technologies, Inc.

    Inventor： Philippe Sartori ,  Deping Liu ,  Brian Classon ,  Qiang Li

    IPC: H04W72/04 ,  H04W56/00 ,  H04W8/00 ,  H04W76/14

    Abstract: A method and system for including a base station that configures a first user equipment (UE) that is in a radio resource control connected state with the base station. The UE is configured to be a synchronization source and transmit a first device-to-device synchronization signal (D2DSS) by using a synchronization resource that comprises a time resource, a frequency resource or a time and frequency resource. The base station instructs the first UE to transmit the first D2DSS using the synchronization resource. The base station signals the UE to configure the UE separately from the signal to transmit the D2DSS, and both of the signals are performed with radio resource control signaling from the base station to the UE.

    Multiple-layer configuration storage for runtime reconfigurable systems
    3.
    发明授权
    Multiple-layer configuration storage for runtime reconfigurable systems 有权

    公开(公告)号：US09853644B2

    公开(公告)日：2017-12-26

    申请号：US15345180

    申请日：2016-11-07

    Applicant: Futurewei Technologies, Inc.

    Inventor： Qiang Wang ,  Zhenguo Gu ,  Zhuolei Wang ,  Qiang Li

    IPC: H03K19/17 ,  H03K19/177 ,  G06F11/10 ,  G06F15/78 ,  H04L12/933

    CPC classification number: H03K19/1776 ,  G06F11/108 ,  G06F15/7867 ,  G06F15/7871 ,  H03K19/17732 ,  H03K19/17756 ,  H04L49/109

    Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

    Multiple-layer configuration storage for runtime reconfigurable systems
    4.
    发明授权
    Multiple-layer configuration storage for runtime reconfigurable systems 有权
    用于运行时可重配置系统的多层配置存储

    公开(公告)号：US09503096B1

    公开(公告)日：2016-11-22

    申请号：US14991579

    申请日：2016-01-08

    Applicant: Futurewei Technologies, Inc.

    Inventor： Qiang Wang ,  Zhenguo Gu ,  Zhuolei Wang ,  Qiang Li

    IPC: H03K19/17 ,  G06F11/10 ,  H03K19/177 ,  G06F15/78 ,  H04L12/933

    CPC classification number: H03K19/1776 ,  G06F11/108 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17756 ,  H04L49/109

    Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

    Abstract translation: 本公开涉及用于配置具有可配置为一个或多个功能模式的多个可编程硬件单元的可编程逻辑器件的技术。 可编程硬件单元耦合到选择存储在公共和共享配置存储器中的配置模式的独立交换设备（例如，多路复用器）。 配置存储器包括一组用于存储配置模式的配置寄存器，哪些配置模式对应于一个或多个功能模式。 可以使用存储在存储器中的地址索引来对配置寄存器进行寻址，以识别特定可编程硬件单元中的一个开关装置中的选择线。 开关装置中的每个选择线对应于存储配置模式的特定配置寄存器。 访问寻址的配置寄存器以检索配置模式并配置可编程硬件单元。

    Reconfigurable data interface unit for compute systems
    10.
    发明授权
    Reconfigurable data interface unit for compute systems 有权

    公开(公告)号：US10185699B2

    公开(公告)日：2019-01-22

    申请号：US15069700

    申请日：2016-03-14

    Applicant: Futurewei Technologies, Inc.

    Inventor： Qiang Wang ,  Zhenguo Gu ,  Qiang Li ,  Zhuolei Wang

    IPC: G06F13/16 ,  G06F15/78 ,  G06F13/42 ,  G06F13/40

    Abstract: A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

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