公开(公告)号：US20180081834A1

公开(公告)日：2018-03-22

申请号：US15703705

申请日：2017-09-13

Applicant: Futurewei Technologies, Inc.

Inventor： Qiang Wang ,  Zhuolei Wang ,  Taneem Ahmed ,  Zhongpin Luo ,  Qiang Li

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4022 ,  G06F13/42 ,  G06F15/7871 ,  G06F15/7892 ,  G06F15/80

Abstract: An apparatus and method are provided for configuring hardware to operate in multiple modes of operation during runtime. Included is a plurality of configurable hardware units each having a plurality of operand inputs for receiving operands, a plurality of outputs for outputting results, and at least one hardware unit configuration input for receiving at least one hardware unit configuration signal. Also included is a configurable interconnect fabric coupled between the configurable hardware units. The configurable interconnect fabric includes a plurality of fabric data inputs and fabric data outputs, and a fabric select input for receiving a fabric select signal. The configurable interconnect fabric is configured to interconnect the configurable hardware units, based on the fabric select signal. A configuration storage configured for containing at least one configuration bit pattern for operating the apparatus in one or more modes of operation and for configuring the hardware during runtime operations.

公开(公告)号：US20170262407A1

公开(公告)日：2017-09-14

申请号：US15069700

申请日：2016-03-14

Applicant: Futurewei Technologies, Inc.

Inventor： Qiang Wang ,  Zhenguo Gu ,  Qiang Li ,  Zhuolei Wang

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F15/7871 ,  G06F13/1673 ,  G06F13/4022 ,  G06F13/4282 ,  G06F15/7817

Abstract: A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

公开(公告)号：US10289598B2

公开(公告)日：2019-05-14

申请号：US15096982

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alex Elisa Chandra ,  YwhPyng Harn ,  Xiaotao Chen ,  Alan Gatherer ,  Fang Yu ,  Xingfeng Chen ,  Zhuolei Wang ,  Yang Zhou

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

公开(公告)号：US10185699B2

公开(公告)日：2019-01-22

申请号：US15069700

申请日：2016-03-14

Applicant: Futurewei Technologies, Inc.

Inventor： Qiang Wang ,  Zhenguo Gu ,  Qiang Li ,  Zhuolei Wang

IPC: G06F13/16 ,  G06F15/78 ,  G06F13/42 ,  G06F13/40

Abstract: A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

公开(公告)号：US09853644B2

公开(公告)日：2017-12-26

申请号：US15345180

申请日：2016-11-07

Applicant: Futurewei Technologies, Inc.

Inventor： Qiang Wang ,  Zhenguo Gu ,  Zhuolei Wang ,  Qiang Li

IPC: H03K19/17 ,  H03K19/177 ,  G06F11/10 ,  G06F15/78 ,  H04L12/933

CPC classification number: H03K19/1776 ,  G06F11/108 ,  G06F15/7867 ,  G06F15/7871 ,  H03K19/17732 ,  H03K19/17756 ,  H04L49/109

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

公开(公告)号：US20170293587A1

公开(公告)日：2017-10-12

申请号：US15096982

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alex Elisa Chandra ,  YwhPyng Harn ,  Xiaotao Chen ,  Alan Gatherer ,  Fang Yu ,  Xingfeng Chen ,  Zhuolei Wang ,  Yang Zhou

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4265 ,  G06F13/4022 ,  G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

Abstract: A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

公开(公告)号：US09503096B1

公开(公告)日：2016-11-22

申请号：US14991579

申请日：2016-01-08

Applicant: Futurewei Technologies, Inc.

Inventor： Qiang Wang ,  Zhenguo Gu ,  Zhuolei Wang ,  Qiang Li

IPC: H03K19/17 ,  G06F11/10 ,  H03K19/177 ,  G06F15/78 ,  H04L12/933

CPC classification number: H03K19/1776 ,  G06F11/108 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17756 ,  H04L49/109

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

Abstract translation: 本公开涉及用于配置具有可配置为一个或多个功能模式的多个可编程硬件单元的可编程逻辑器件的技术。 可编程硬件单元耦合到选择存储在公共和共享配置存储器中的配置模式的独立交换设备（例如，多路复用器）。 配置存储器包括一组用于存储配置模式的配置寄存器，哪些配置模式对应于一个或多个功能模式。 可以使用存储在存储器中的地址索引来对配置寄存器进行寻址，以识别特定可编程硬件单元中的一个开关装置中的选择线。 开关装置中的每个选择线对应于存储配置模式的特定配置寄存器。 访问寻址的配置寄存器以检索配置模式并配置可编程硬件单元。