公开(公告)号：US20250023464A1

公开(公告)日：2025-01-16

申请号：US18350664

申请日：2023-07-11

Applicant: GAN SYSTEMS INC.

Inventor： Krishnaswamy NAGARAJ ,  Nan XING ,  Sridhar RAMASWAMY ,  Edward MACROBBIE ,  Robert Wayne MOUNGER ,  Lucas Andrew MILNER

IPC: H02M3/07

Abstract: A voltage supply circuit that generates a voltage on a voltage supply node. The voltage supply circuit includes an adjustable capacitor, an alternating voltage source, a charge source, and an adjusting circuit. When the alternating voltage on the second capacitor terminal transitions low, the voltage on the first capacitor terminal also becomes low, and the charge source provides charge to the first capacitor terminal of the adjustable capacitor. When the alternating voltage on the second capacitor terminal transitions high, the voltage on the first capacitor terminal also becomes high, and charge is thereby pumped from the first capacitor terminal to the voltage supply node. The adjusting circuit periodically samples the voltage on the voltage supply node, and adjusts the capacitance of the adjustable capacitor to increase or decrease that voltage.

公开(公告)号：US20230198252A1

公开(公告)日：2023-06-22

申请号：US17975092

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Edward MACROBBIE

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

Abstract: A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

公开(公告)号：US20240405768A1

公开(公告)日：2024-12-05

申请号：US18327620

申请日：2023-06-01

Applicant: GAN SYSTEMS INC.

Inventor： Nan XING ,  Robert Wayne MOUNGER ,  Lucas Andrew MILNER ,  Krishnaswamy NAGARAJ ,  Sridhar RAMASWAMY ,  Yinglai XIA ,  Edward MACROBBIE

IPC: H03K17/687

Abstract: A power transistor circuit suppling an internal voltage to an internal voltage supply node. The power transistor circuit includes external terminals, to each of which signals and/or voltages are applied, for each of the input node, output node and control node of the power transistor. The power transistor circuit includes the power transistor, a current draw transistor, a first diode connected between an external control terminal and the internal voltage supply node, and a second diode connected between the current draw transistor output node and the internal voltage supply node. The power transistor circuit includes a charge pump that receives power from the internal voltage supply node and outputs a voltage to the control node of the current draw transistor. In operation, the internal voltage supply node receives power from the external control terminal via the first diode, or an external input terminal via the current draw transistor and the second diode.

公开(公告)号：US20240393374A1

公开(公告)日：2024-11-28

申请号：US18322441

申请日：2023-05-23

Applicant: GAN SYSTEMS INC.

Inventor： Lucas Andrew MILNER ,  Marco A. ZUNIGA ,  Nan XING ,  Robert Wayne MOUNGER ,  Edward MACROBBIE ,  Sridhar RAMASWAMY ,  Ahmad MIZANNOJEHDEHI ,  Thomas William MACELWEE

IPC: G01R19/00

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

公开(公告)号：US20230050580A1

公开(公告)日：2023-02-16

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein MOUSAVIAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/861 ,  H01L29/778 ,  H01L29/417

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact to pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US20230050485A1

公开(公告)日：2023-02-16

申请号：US17974880

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

公开(公告)号：US20220139810A1

公开(公告)日：2022-05-05

申请号：US17117449

申请日：2020-12-10

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/778

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

公开(公告)号：US20220139809A1

公开(公告)日：2022-05-05

申请号：US17085137

申请日：2020-10-30

Applicant: GaN Systems Inc.

Inventor： Hossein MOUSAVIAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/861

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.