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    FABRICATION OF EMBEDDED DIE PACKAGING COMPRISING LASER DRILLED VIAS
    1.
    发明申请
    FABRICATION OF EMBEDDED DIE PACKAGING COMPRISING LASER DRILLED VIAS 有权

    公开(公告)号：US20230019052A1

    公开(公告)日：2023-01-19

    申请号：US17945231

    申请日：2022-09-15

    Applicant: GaN Systems Inc.

    Inventor： Cameron MCKNIGHT-MACNEIL ,  Abhinandan DIXIT ,  Ahmad MIZAN ,  An-Sheng CHENG

    IPC: H01L23/00 ,  B23K26/06 ,  B23K26/364 ,  B23K26/60

    Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to protect against over-drilling and/or to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating physical damage, overheating or other potential damage to the semiconductor device. The masking layer may be resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS
    2.
    发明申请
    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS 审中-公开

    公开(公告)号：US20200091291A1

    公开(公告)日：2020-03-19

    申请号：US16688008

    申请日：2019-11-19

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Hossein MOUSAVIAN ,  Xiaodong CUI

    IPC: H01L29/06 ,  H01L29/205 ,  H01L23/522 ,  H01L23/528 ,  H01L23/482 ,  H01L29/423

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

    SOLDER RESIST STRUCTURE FOR EMBEDDED DIE PACKAGING OF POWER SEMICONDUCTOR DEVICES
    3.
    发明申请
    SOLDER RESIST STRUCTURE FOR EMBEDDED DIE PACKAGING OF POWER SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220416069A1

    公开(公告)日：2022-12-29

    申请号：US17358349

    申请日：2021-06-25

    Applicant: GaN Systems Inc.

    Inventor： Cameron MCKNIGHT-MACNEIL ,  Ahmad MIZAN ,  Maryam ABOUIE

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L23/00

    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS
    4.
    发明申请
    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS 审中-公开

    公开(公告)号：US20190081141A1

    公开(公告)日：2019-03-14

    申请号：US15988453

    申请日：2018-05-24

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Hossein MOUSAVIAN ,  Xiaodong CUI

    IPC: H01L29/06 ,  H01L23/482 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/40 ,  H01L23/522 ,  H01L23/528

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    5.
    发明申请
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 有权
    用于大面积氮化物半导体器件的容错设计

    公开(公告)号：US20160284829A1

    公开(公告)日：2016-09-29

    申请号：US15032824

    申请日：2014-10-28

    Applicant: GAN SYSTEMS INC.

    Inventor： Greg P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL ,  Howard TWEDDLE ,  Ahmad MIZAN ,  Nigel SPRINGETT

    IPC: H01L29/778 ,  H01L21/66 ,  H01L29/16 ,  H01L29/417 ,  H01L29/205 ,  H01L29/861 ,  H01L29/20 ,  H01L29/06

    CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    Abstract translation: 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，漏电极并联，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛屿提供互连，同时电隔离有缺陷的岛屿。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    7.
    发明申请
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 有权
    用于大面积氮化物半导体器件的容错设计

    公开(公告)号：US20150162252A1

    公开(公告)日：2015-06-11

    申请号：US14568507

    申请日：2014-12-12

    Applicant: GAN SYSTEMS INC.

    Inventor： Gregory P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL ,  Howard TWEDDLE ,  Ahmad MIZAN ,  Nigel SPRINGETT

    IPC: H01L21/66 ,  H01L29/201 ,  H01L23/528 ,  H01L29/778 ,  H01L27/095 ,  H01L29/20 ,  H01L29/205

    CPC classification number: H01L29/7787 ,  H01L22/14 ,  H01L22/22 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    Abstract translation: 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，漏电极并联，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛屿提供互连，同时电隔离有缺陷的岛屿。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。

    DUAL-SIDE COOLED EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES
    8.
    发明公开
    DUAL-SIDE COOLED EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230402342A1

    公开(公告)日：2023-12-14

    申请号：US18094477

    申请日：2023-01-09

    Applicant: GaN Systems Inc.

    Inventor： Di CHEN ,  Juncheng LU ,  Ahmad MIZAN ,  Ruoyu HOU ,  Abhinandan DIXIT

    IPC: H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

    CPC classification number: H01L23/3672 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.

    INTEGRATED BIDIRECTIONAL ESD PROTECTION CIRCUIT FOR POWER SEMICONDUCTOR SWITCHING DEVICES
    9.
    发明公开
    INTEGRATED BIDIRECTIONAL ESD PROTECTION CIRCUIT FOR POWER SEMICONDUCTOR SWITCHING DEVICES 审中-公开

    公开(公告)号：US20230198252A1

    公开(公告)日：2023-06-22

    申请号：US17975092

    申请日：2022-10-27

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Edward MACROBBIE

    IPC: H02H9/04 ,  H01L27/02

    CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

    Abstract: A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS
    10.
    发明申请
    SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS 有权

    公开(公告)号：US20210367035A1

    公开(公告)日：2021-11-25

    申请号：US17393846

    申请日：2021-08-04

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Hossein MOUSAVIAN ,  Xiaodong CUI

    IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/423

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise source, drain and gate finger electrodes on active regions of a plurality of sections of a multi-section transistor, and a contact structure comprising source and drain contact areas, e.g. drain and source pads extending over active regions of each section, interconnected by conductive micro-vias to respective underlying drain and source finger electrodes. Alternatively, source contact areas comprise parts of a source bus which runs over inactive regions. For reduced gate loop inductance, the source bus may be routed over or under the to gate bus. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of the drain finger electrodes. Example CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

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