公开(公告)号：US20150076624A1

公开(公告)日：2015-03-19

申请号：US14031839

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huang Liu ,  Jialin Yu ,  Jilin Xia

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L21/32115 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

Abstract translation: 提供了具有平滑金属栅极的集成电路和用于制造具有光滑金属栅极的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供部分制造的集成电路，其包括由沟槽表面限定的沟槽形成的电介质层。 该方法将金属沉积在沟槽中并形成覆盖在介电层上的金属覆盖层部分。 该方法包括用化学蚀刻剂选择性地蚀刻金属并去除金属的覆盖层部分。

公开(公告)号：US09230863B2

公开(公告)日：2016-01-05

申请号：US14177854

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jialin Yu ,  Huang Liu ,  Jilin Xia ,  Girish Bohra

IPC: H01L21/4763 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.

Abstract translation: 提供具有光滑表面的钨成分的集成电路以及用于制造这种集成电路的方法。 一种制造集成电路的方法包括形成层叠在基底上的成核层，并且其中成核层包含钨。 成核层厚度减小，填充层如果形成在成核层上方。

公开(公告)号：US08859417B2

公开(公告)日：2014-10-14

申请号：US13733282

申请日：2013-01-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jialin Yu ,  Huang Liu ,  Jilin Xia

IPC: H01L21/4763 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductive structure(s), such as a gate electrode(s) or a contact structure(s), and methods of fabrication thereof are provided. The conductive structure(s) includes a first conductive layer of a first conductive material, and a second conductive layer of a second conductive material. The second conductive layer is disposed over the first conductive layer, and at least a portion of the first conductive material includes grains having a size larger than a defined value, and at least a second portion of the second conductive material includes grains having a size less than the defined value. In one embodiment, the first and second conductive materials are the same conductive material, with different-sized grains.

Abstract translation: 提供导电结构，例如栅电极或接触结构，以及其制造方法。 导电结构包括第一导电材料的第一导电层和第二导电材料的第二导电层。 第二导电层设置在第一导电层上，并且第一导电材料的至少一部分包括尺寸大于限定值的晶粒，并且第二导电材料的至少第二部分包括尺寸较小的晶粒 比定义的值。 在一个实施例中，第一和第二导电材料是相同的导电材料，具有不同尺寸的晶粒。

公开(公告)号：US20150228543A1

公开(公告)日：2015-08-13

申请号：US14177854

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jialin Yu ,  Huang Liu ,  Jilin Xia ,  Girish Bohra

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.

Abstract translation: 提供具有光滑表面的钨成分的集成电路以及用于制造这种集成电路的方法。 一种制造集成电路的方法包括形成层叠在基底上的成核层，并且其中成核层包含钨。 成核层厚度减小，填充层如果形成在成核层上方。