Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
    1.
    发明授权
    Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes 有权
    形成集成电路和多重临界尺寸自对准双重图案化工艺的方法

    公开(公告)号:US09431264B2

    公开(公告)日:2016-08-30

    申请号:US14014906

    申请日:2013-08-30

    Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

    Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法,其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴,其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

    METHODS OF FORMING INTEGRATED CIRCUITS AND MULTIPLE CRITICAL DIMENSION SELF-ALIGNED DOUBLE PATTERNING PROCESSES
    2.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUITS AND MULTIPLE CRITICAL DIMENSION SELF-ALIGNED DOUBLE PATTERNING PROCESSES 有权
    形成集成电路的方法和多重关键尺寸自对准的双向绘图工艺

    公开(公告)号:US20150064912A1

    公开(公告)日:2015-03-05

    申请号:US14014906

    申请日:2013-08-30

    Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

    Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法,其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴,其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

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