公开(公告)号：US20180053743A1

公开(公告)日：2018-02-22

申请号：US15239976

申请日：2016-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L27/0694 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

公开(公告)号：US10276461B2

公开(公告)日：2019-04-30

申请号：US15665974

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00

Abstract: A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material.

公开(公告)号：US10049979B2

公开(公告)日：2018-08-14

申请号：US15292721

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Ian D. W. Melville

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.

公开(公告)号：US10068899B2

公开(公告)日：2018-09-04

申请号：US15239976

申请日：2016-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L27/06 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

公开(公告)号：US20180108607A1

公开(公告)日：2018-04-19

申请号：US15292721

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Ian D. W. Melville

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53276

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.