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    METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES
    1.
    发明申请
    METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES 审中-公开

    公开(公告)号：US20190131424A1

    公开(公告)日：2019-05-02

    申请号：US15801722

    申请日：2017-11-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Guowei Xu ,  Suraj K. Patil ,  Hui Zang ,  Katsunori Onishi ,  Keith H. Tabakman

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

    Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.

    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    3.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08779525B2

    公开(公告)日：2014-07-15

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    4.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20130161759A1

    公开(公告)日：2013-06-27

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

    GATE CUT FIRST ISOLATION FORMATION WITH CONTACT FORMING PROCESS MASK PROTECTION
    6.
    发明申请
    GATE CUT FIRST ISOLATION FORMATION WITH CONTACT FORMING PROCESS MASK PROTECTION 审中-公开

    公开(公告)号：US20200266286A1

    公开(公告)日：2020-08-20

    申请号：US16280343

    申请日：2019-02-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiaoming Yang ,  Sipeng Gu ,  Jeffrey Chee ,  Keith H. Tabakman

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

    Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

    APPARATUS AND METHOD FOR ALIGNING INTEGRATED CIRCUIT LAYERS USING MULTIPLE GRATING MATERIALS
    7.
    发明申请
    APPARATUS AND METHOD FOR ALIGNING INTEGRATED CIRCUIT LAYERS USING MULTIPLE GRATING MATERIALS 有权

    公开(公告)号：US20200152498A1

    公开(公告)日：2020-05-14

    申请号：US16188814

    申请日：2018-11-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Dongyue Yang ,  Keith H. Tabakman ,  Guanchen He ,  Xintuo Dai ,  Xueli Hao

    IPC: H01L21/68 ,  H01L21/033 ,  H01L21/762 ,  H01L23/544

    Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

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