公开(公告)号：US10236358B1

公开(公告)日：2019-03-19

申请号：US15784445

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Jagar Singh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02

Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. The structure includes a gate structure having a sidewall and a sidewall spacer arranged adjacent to the sidewall of the gate structure. The sidewall spacer includes an energy removal film material and one or more air gaps in the energy removal film material.

公开(公告)号：US09698241B1

公开(公告)日：2017-07-04

申请号：US15071600

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Suraj K. Patil ,  Min-Hwa Chi ,  Mitsuhiro Togo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

公开(公告)号：US09620381B2

公开(公告)日：2017-04-11

申请号：US14050472

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Huy Cao ,  Hui Zhan ,  Huang Liu

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L21/31105 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

公开(公告)号：US20160351675A1

公开(公告)日：2016-12-01

申请号：US14721822

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Suraj K. Patil ,  Mitsuhiro Togo

IPC: H01L29/423 ,  H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/225

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes defining a pFET region and an nFET region of a semiconductor substrate. The method deposits a first work function material including tungsten and nitride over the pFET region and the nFET region of the semiconductor substrate. The method includes selectively modifying the first work function material in a selected region. Further, the method includes depositing a metal fill over the first work function material in the pFET region and the nFET region of the semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括限定半导体衬底的pFET区和nFET区。 该方法在pFET区域和半导体衬底的nFET区域上沉积包括钨和氮化物的第一功函材料。 该方法包括选择性地修改选定区域中的第一功函数材料。 此外，该方法包括在pFET区域和半导体衬底的nFET区域中的第一功函数材料上沉积金属填充物。

公开(公告)号：US09396995B1

公开(公告)日：2016-07-19

申请号：US14634080

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Garo Derderian ,  Wen-Pin Peng

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/263 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/49

CPC classification number: H01L21/7684 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/456

Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.

Abstract translation: 提供了一种在MOL中形成金属化接触的方法。 实施例包括通过ILD形成TT到S / D区域; 在TT的侧表面上形成SiOC，SiCN或SiON层; 以0°角执行GCIB垂直蚀刻; 通过角度PAI将Si注入TT; 通过Ar溅射和远程等离子体辅助干蚀刻工艺去除TT的一部分; 在TT底部的S / D区域形成NiSi; 并用NiSi上的接触金属填充TT。

公开(公告)号：US09195132B2

公开(公告)日：2015-11-24

申请号：US14168396

申请日：2014-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  SherJang Singh ,  Uzodinma Okoroanyanwu ,  Obert R. Wood ,  Pawitter J. S. Mangat

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: A lithography mask structure is provided, including: a substrate; at least one reflective layer over the substrate; and an absorber film stack over the at least one reflective layer, the absorber film stack including a plurality of first film layers of a first material and at least one second film layer of a second material. The second material is different from the first material, and the second film layer(s) is interleaved with the plurality of first film layers. In one embodiment, the total thickness of the absorber film stack is less than 50 nm. In another embodiment, the reflectivity of the absorber film stack is less than 2% for a pre-defined wavelength of EUV light. In a further embodiment, the second film layer(s) prevents the average crystallite size of the first film layers from exceeding the thickness of the first film layers.

Abstract translation: 提供光刻掩模结构，包括：基板; 衬底上的至少一个反射层; 以及在所述至少一个反射层上的吸收膜叠层，所述吸收膜叠层包括多个第一材料的第一膜层和至少一个第二材料的第二膜层。 第二材料与第一材料不同，并且第二膜层与多个第一膜层交错。 在一个实施例中，吸收膜叠层的总厚度小于50nm。 在另一个实施例中，对于预定波长的EUV光，吸收膜叠层的反射率小于2％。 在另一实施例中，第二膜层防止第一膜层的平均微晶尺寸超过第一膜层的厚度。

公开(公告)号：US20190131424A1

公开(公告)日：2019-05-02

申请号：US15801722

申请日：2017-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Suraj K. Patil ,  Hui Zang ,  Katsunori Onishi ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US10056331B2

公开(公告)日：2018-08-21

申请号：US15724563

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Suraj K. Patil ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US20180012791A1

公开(公告)日：2018-01-11

申请号：US15202867

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Suraj K. Patil ,  Jiehui Shu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063

Abstract: Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to define an air gap located inside the opening in the dielectric layer. The air gap is located between the conductive plug and the opening in the dielectric layer.