公开(公告)号：US20180286863A1

公开(公告)日：2018-10-04

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US10020307B1

公开(公告)日：2018-07-10

申请号：US15429502

申请日：2017-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L21/8249 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.

公开(公告)号：US10396078B2

公开(公告)日：2019-08-27

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US20180090391A1

公开(公告)日：2018-03-29

申请号：US15274974

申请日：2016-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC classification number: H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

公开(公告)号：US09960086B2

公开(公告)日：2018-05-01

申请号：US15274974

申请日：2016-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC: H01L21/31 ,  H01L21/82 ,  H01L21/30 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC classification number: H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.