公开(公告)号：US09251890B1

公开(公告)日：2016-02-02

申请号：US14577113

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Navin Agarwal ,  Igor Arsovski ,  Venkatraghavan Bringivijayaraghavan ,  Krishnan S. Rengarajan

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/10 ,  G11C7/04 ,  G11C11/4096 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/109 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/06 ,  G11C29/12015

Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Abstract translation: 具有年龄检测和校正（ADAC）电路的存储器件，其检测由偏置温度不稳定性疲劳引起的偏差（即，随时间累积的偏置温度不稳定性应力），并且通过选择性地调整比例（在时间上测量）来计数偏斜， 的活动状态操作到空闲状态操作。 另外，使用类似的ADAC电路的存储器老化装置。

公开(公告)号：US09589658B1

公开(公告)日：2017-03-07

申请号：US14828770

申请日：2015-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navin Agarwal ,  Aditya S. Auyisetty ,  Balaji Jayaraman ,  Thejas Kempanna ,  Toshiaki Kirihata ,  Ramesh Raghavan ,  Krishnan S. Rengarajan ,  Rajesh R. Tummuru ,  Jay M. Shah ,  Janakiraman Viraraghavan

IPC: G11C16/22 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C7/02 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C17/14 ,  G11C17/18

Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

Abstract translation: 提供了包括单元阵列的存储器的方法。 存储器包括连接到位线和节点并由字线控制的单元阵列的第一器件和单元阵列的第二器件，其包括连接到源极线和该节点的第三器件，以及 由字线控制，第四器件连接在字线和节点之间。 在存储器中，响应于单元阵列中的另一个字线被激活并且字线未被激活以保持第一器件处于未编程状态，第三器件隔离并漂浮该节点，使得栅极的电压电平 第一器件的源极被第四器件钳位到零电压附近的电压电平。