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公开(公告)号：US20170162234A1
公开(公告)日：2017-06-08
申请号：US14961484
申请日：2015-12-07
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ramesh Raghavan , Balaji Jayaraman , Janakiraman Viraraghavan , Thejas Kempanna , Rajesh Reddy Tummuru , Toshiaki Kirihata
CPC classification number: G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C2207/002 , G11C2211/4013
Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.
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公开(公告)号：US09659604B1
公开(公告)日：2017-05-23
申请号：US14961484
申请日：2015-12-07
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ramesh Raghavan , Balaji Jayaraman , Janakiraman Viraraghavan , Thejas Kempanna , Rajesh Reddy Tummuru , Toshiaki Kirihata
CPC classification number: G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C2207/002 , G11C2211/4013
Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.
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公开(公告)号：US20170256468A1
公开(公告)日：2017-09-07
申请号：US15062484
申请日：2016-03-07
Applicant: GLOBALFOUNDRIES INC.
Inventor： Janakiraman Viraraghavan , Ramesh Raghavan , Balaji Jayaraman , Thejas Kempanna , Rajesh R. Tummuru , Toshiaki Kirihata
IPC: H01L21/66 , H01L27/105 , H01L49/02 , H01L27/115
CPC classification number: H01L22/32 , H01L22/14 , H01L22/20 , H01L22/22 , H01L27/1052 , H01L27/115 , H01L28/40
Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.
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公开(公告)号：US09721673B1
公开(公告)日：2017-08-01
申请号：US15363056
申请日：2016-11-29
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ramesh Raghavan , Balaji Jayaraman , Rajesh R. Tummuru , Thejas Kempanna , Janakiraman Viraraghavan
CPC classification number: G11C17/18 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.
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公开(公告)号：US09589658B1
公开(公告)日：2017-03-07
申请号：US14828770
申请日：2015-08-18
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Navin Agarwal , Aditya S. Auyisetty , Balaji Jayaraman , Thejas Kempanna , Toshiaki Kirihata , Ramesh Raghavan , Krishnan S. Rengarajan , Rajesh R. Tummuru , Jay M. Shah , Janakiraman Viraraghavan
CPC classification number: G11C16/3427 , G11C7/02 , G11C16/0466 , G11C16/0475 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/28 , G11C17/14 , G11C17/18
Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.
Abstract translation: 提供了包括单元阵列的存储器的方法。 存储器包括连接到位线和节点并由字线控制的单元阵列的第一器件和单元阵列的第二器件，其包括连接到源极线和该节点的第三器件，以及 由字线控制，第四器件连接在字线和节点之间。 在存储器中，响应于单元阵列中的另一个字线被激活并且字线未被激活以保持第一器件处于未编程状态，第三器件隔离并漂浮该节点，使得栅极的电压电平 第一器件的源极被第四器件钳位到零电压附近的电压电平。
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Patent Agency Ranking
公开(公告)号：US09859177B2
公开(公告)日：2018-01-02
申请号：US15062484
申请日：2016-03-07
Applicant: GLOBALFOUNDRIES INC.
Inventor： Janakiraman Viraraghavan , Ramesh Raghavan , Balaji Jayaraman , Thejas Kempanna , Rajesh R. Tummuru , Toshiaki Kirihata
IPC: G11C7/00 , H01L21/66 , H01L27/115 , H01L27/105 , H01L49/02
CPC classification number: H01L22/32 , H01L22/14 , H01L22/20 , H01L22/22 , H01L27/1052 , H01L27/115 , H01L28/40
Abstract: Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.
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公开(公告)号：US09786333B2
公开(公告)日：2017-10-10
申请号：US15478820
申请日：2017-04-04
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ramesh Raghavan , Balaji Jayaraman , Janakiraman Viraraghavan , Thejas Kempanna , Rajesh Reddy Tummuru , Toshiaki Kirihata
CPC classification number: G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C2207/002 , G11C2211/4013
Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.
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公开(公告)号：US09721059B1
公开(公告)日：2017-08-01
申请号：US15002808
申请日：2016-01-21
Applicant: GLOBALFOUNDRIES INC.
Inventor： Tamilmani Ethirajan , Ashwin Srinivas , Ananth Sundaram , Janakiraman Viraraghavan
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/5036 , G06F2217/80
Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist. The electrical and thermal netlists are combined and simulations are performed on the combined electrical-thermal netlist in order to generate a thermal-aware performance model of the IC.
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公开(公告)号：US20170212978A1
公开(公告)日：2017-07-27
申请号：US15002808
申请日：2016-01-21
Applicant: GLOBALFOUNDRIES INC.
Inventor： Tamilmani Ethirajan , Ashwin Srinivas , Ananth Sundaram , Janakiraman Viraraghavan
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/5036 , G06F2217/80
Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist. The electrical and thermal netlists are combined and simulations are performed on the combined electrical-thermal netlist in order to generate a thermal-aware performance model of the IC.
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公开(公告)号：US20170206938A1
公开(公告)日：2017-07-20
申请号：US15478820
申请日：2017-04-04
Applicant: GLOBALFOUNDRIES INC.
Inventor： Ramesh Raghavan , Balaji Jayaraman , Janakiraman Viraraghavan , Thejas Kempanna , Rajesh Reddy Tummuru , Toshiaki Kirihata
CPC classification number: G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C2207/002 , G11C2211/4013
Abstract: A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.
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