公开(公告)号：US20180175266A1

公开(公告)日：2018-06-21

申请号：US15385068

申请日：2016-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke ENGLAND ,  Rahul AGARWAL

IPC: H01L33/62 ,  H01L33/30 ,  H01L33/32 ,  H01L33/28 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L33/62 ,  F21V19/005 ,  F21Y2115/10 ,  H01L24/80 ,  H01L25/167 ,  H01L33/28 ,  H01L33/30 ,  H01L33/32 ,  H01L2224/80896

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to wafer bond interconnect structures and methods of manufacture. The structure includes: a plurality of sub-pixels each comprising a contact plate; and redundant connections at opposite corners of each sub-pixel on a backside of the contact plate.

公开(公告)号：US20180076110A1

公开(公告)日：2018-03-15

申请号：US15264957

申请日：2016-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul AGARWAL ,  Luke ENGLAND ,  Haojun ZHANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/288

CPC classification number: H01L23/3675 ,  H01L21/2885 ,  H01L21/4871 ,  H01L23/3677 ,  H01L23/42 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26122 ,  H01L2224/27011 ,  H01L2224/32245 ,  H01L2224/83007 ,  H01L2924/14

Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

公开(公告)号：US20190019915A1

公开(公告)日：2019-01-17

申请号：US15650427

申请日：2017-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinivasa BANNA ,  Deepak NAYAK ,  Luke ENGLAND ,  Rahul AGARWAL

IPC: H01L31/18 ,  H01L27/15

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.