公开(公告)号：US20190067217A1

公开(公告)日：2019-02-28

申请号：US15685564

申请日：2017-08-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

公开(公告)号：US10236263B1

公开(公告)日：2019-03-19

申请号：US15685564

申请日：2017-08-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke England ,  Tanya Atanasova ,  Daniel Smith ,  Daniel Fisher ,  Sukeshwar Kannan

IPC: H01L23/60 ,  H01L23/522 ,  H01L23/00

Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

公开(公告)号：US10083958B2

公开(公告)日：2018-09-25

申请号：US15292488

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sukeshwar Kannan ,  Somnath Ghosh ,  Daniel Smith ,  Luke England

IPC: H01L27/06 ,  H01L23/66 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0682 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/20 ,  H01L28/55 ,  H01L28/60 ,  H01L2223/6672

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

公开(公告)号：US09917009B2

公开(公告)日：2018-03-13

申请号：US15228317

申请日：2016-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.

公开(公告)号：US09349608B2

公开(公告)日：2016-05-24

申请号：US14106340

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Daniel Smith ,  Kumarapuram Gopalakrishnan ,  Hung-Wei Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/29 ,  H01L21/308 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/32051 ,  H01L21/3081 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with a protection layer for a dielectric mask layer are provided. One method includes, for instance; obtaining a substrate having at least one of a dielectric layer and a metal layer; forming a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and forming a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer. One intermediate semiconductor device includes, for instance: a substrate having at least one of a dielectric layer and a metal layer; a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer.

Abstract translation: 提供了用于形成具有用于介电掩模层的保护层的半导体器件的器件和方法。 一种方法包括： 获得具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上形成第一SiCN电介质掩模层; 以及在所述第一SiCN介电掩模层的顶表面上形成氮化硅（SiNx）覆盖层。 一个中间半导体器件包括例如：具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上的第一SiCN介电掩模层; 和在第一SiCN介电掩模层的顶表面上的氮化硅（SiNx）覆盖层。

公开(公告)号：US10446443B2

公开(公告)日：2019-10-15

申请号：US15877549

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L23/532 ,  H01L29/423 ,  H01L29/417 ,  H01L23/485 ,  H01L23/522

Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.

公开(公告)号：US20180158733A1

公开(公告)日：2018-06-07

申请号：US15877549

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/306 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.

公开(公告)号：US20180108651A1

公开(公告)日：2018-04-19

申请号：US15292488

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sukeshwar Kannan ,  Somnath Ghosh ,  Daniel Smith ,  Luke England

IPC: H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L27/0682 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/20 ,  H01L28/55 ,  H01L28/60 ,  H01L2223/6672

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

公开(公告)号：US20180040511A1

公开(公告)日：2018-02-08

申请号：US15228317

申请日：2016-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/768 ,  H01L29/423 ,  H01L21/306 ,  H01L23/532 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.