公开(公告)号：US10084057B2

公开(公告)日：2018-09-25

申请号：US15237794

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Martin Trentzsch ,  Stefan Flachowsky ,  Axel Henke

IPC: H03K3/01 ,  H01L29/51 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/40111 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78391 ,  H01L29/78654

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

公开(公告)号：US20180053832A1

公开(公告)日：2018-02-22

申请号：US15237794

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Martin Trentzsch ,  Stefan Flachowsky ,  Axel Henke

IPC: H01L29/51 ,  H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78391 ,  H01L29/786

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.