公开(公告)号：US09299584B2

公开(公告)日：2016-03-29

申请号：US14314595

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dinesh Koli ,  Deepasree Konduparthi

IPC: H01L21/4763 ,  H01L21/321 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L21/3212 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.

Abstract translation: 提供了形成集成电路的器件和方法以及具有平坦化永久层的FinFET器件。 在一个实施例中，形成平坦化永久层的方法包括提供具有不平坦表面形貌的基底。 永久层在基底基材上共形地形成。 永久层包括对应于基底基板的表面形貌的凸起部分和下沉部分。 在永久层上共形形成牺牲层。 永久层的牺牲层和凸起部分被化学机械平面化以提供平坦化的永久层。 在化学机械平面化之后基本上完全去除牺牲层。

公开(公告)号：US20150380269A1

公开(公告)日：2015-12-31

申请号：US14314595

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dinesh Koli ,  Deepasree Konduparthi

IPC: H01L21/321 ,  H01L27/088 ,  H01L21/3105

CPC classification number: H01L21/3212 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.

Abstract translation: 提供了形成集成电路的器件和方法以及具有平坦化永久层的FinFET器件。 在一个实施例中，形成平坦化永久层的方法包括提供具有不平坦表面形貌的基底。 永久层在基底基材上共形地形成。 永久层包括对应于基底基板的表面形貌的凸起部分和下沉部分。 在永久层上共形形成牺牲层。 永久层的牺牲层和凸起部分被化学机械平面化以提供平坦化的永久层。 在化学机械平面化之后基本上完全去除牺牲层。

公开(公告)号：US09159567B1

公开(公告)日：2015-10-13

申请号：US14259497

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Changyong Xiao ,  Hoong Shing Wong ,  Deepasree Konduparthi ,  Rohit Pal

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract translation: 一种方法包括提供具有虚拟栅极的栅极结构，沿栅极侧面的第一间隔物。 去除虚拟栅极和间隔物以露出栅极电介质。 第二间隔物沉积在栅极结构腔的至少一侧和栅极电介质的顶部。 去除第二间隔件的底部以暴露栅极电介质，并且将栅极结构湿式清洁。

公开(公告)号：US09136131B2

公开(公告)日：2015-09-15

申请号：US14071044

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deepasree Konduparthi ,  Dinesh Koli

IPC: H01L21/3205 ,  H01L21/283 ,  H01L21/28 ,  H01L29/49 ,  H01L29/45

CPC classification number: H01L21/283 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575

Abstract: A semiconductor structure includes a source region, a drain region, a channel region and a gate region over a bulk silicon substrate. The gate region further includes a dielectric layer and one or more work function layers disposed over the dielectric layer. A first filler material, such as a flowable oxide is provided over the source region and the drain region. A second filler material, such as an organic material, is provided within the gate region. The first filler material and the second filler material are selectively removed to create, source, drain and gate openings. The gate, source and drain openings are filled simultaneously with a metal, such as tungsten, to create a metal gate structure, source contact and drain contact.

Abstract translation: 半导体结构包括源区域，漏极区域，沟道区域和体硅衬底上的栅极区域。 栅极区域还包括介电层和设置在电介质层上的一个或多个功函数层。 在源极区域和漏极区域上设置有诸如可流动氧化物的第一填充材料。 在栅极区域内提供第二种填充材料，例如有机材料。 选择性地去除第一填充材料和第二填充材料以产生，源极，漏极和栅极开口。 栅极，源极和漏极开口与诸如钨的金属同时填充以产生金属栅极结构，源极接触和漏极接触。