公开(公告)号：US20150200111A1

公开(公告)日：2015-07-16

申请号：US14153120

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sruthi Muralidharan ,  Zhenyu Hu ,  Qi Zhang ,  Ja-Hyung Han ,  Dinesh Koli ,  Zhuangfei Chen

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/32115 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity.

Abstract translation: 本发明的实施例提供了用于制造finFET的改进方法。 在finFET制造期间，诸如非晶硅的膜沉积在半导体衬底上，该半导体衬底具有鳍片和不具有鳍片的区域。 填充层沉积在膜上并且被平坦化以形成齐平表面。 使用凹陷或蚀刻工艺来形成平坦表面，其中填充层的所有部分被去除。 可以使用诸如气体簇离子束工艺的精加工工艺来进一步平滑衬底表面。 这导致在结构（例如半导体晶片）上具有非常均匀的厚度的膜，导致晶片内（WiW）的均匀性提高和芯片内（WiC）均匀性提高。

公开(公告)号：US09136131B2

公开(公告)日：2015-09-15

申请号：US14071044

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deepasree Konduparthi ,  Dinesh Koli

IPC: H01L21/3205 ,  H01L21/283 ,  H01L21/28 ,  H01L29/49 ,  H01L29/45

CPC classification number: H01L21/283 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575

Abstract: A semiconductor structure includes a source region, a drain region, a channel region and a gate region over a bulk silicon substrate. The gate region further includes a dielectric layer and one or more work function layers disposed over the dielectric layer. A first filler material, such as a flowable oxide is provided over the source region and the drain region. A second filler material, such as an organic material, is provided within the gate region. The first filler material and the second filler material are selectively removed to create, source, drain and gate openings. The gate, source and drain openings are filled simultaneously with a metal, such as tungsten, to create a metal gate structure, source contact and drain contact.

Abstract translation: 半导体结构包括源区域，漏极区域，沟道区域和体硅衬底上的栅极区域。 栅极区域还包括介电层和设置在电介质层上的一个或多个功函数层。 在源极区域和漏极区域上设置有诸如可流动氧化物的第一填充材料。 在栅极区域内提供第二种填充材料，例如有机材料。 选择性地去除第一填充材料和第二填充材料以产生，源极，漏极和栅极开口。 栅极，源极和漏极开口与诸如钨的金属同时填充以产生金属栅极结构，源极接触和漏极接触。

公开(公告)号：US10020260B1

公开(公告)日：2018-07-10

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Benjamin G. Moser ,  Vimal Kumar Kamineni ,  Dinesh Koli ,  Vishal Chhabra

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

公开(公告)号：US20150380269A1

公开(公告)日：2015-12-31

申请号：US14314595

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dinesh Koli ,  Deepasree Konduparthi

IPC: H01L21/321 ,  H01L27/088 ,  H01L21/3105

CPC classification number: H01L21/3212 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.

Abstract translation: 提供了形成集成电路的器件和方法以及具有平坦化永久层的FinFET器件。 在一个实施例中，形成平坦化永久层的方法包括提供具有不平坦表面形貌的基底。 永久层在基底基材上共形地形成。 永久层包括对应于基底基板的表面形貌的凸起部分和下沉部分。 在永久层上共形形成牺牲层。 永久层的牺牲层和凸起部分被化学机械平面化以提供平坦化的永久层。 在化学机械平面化之后基本上完全去除牺牲层。

公开(公告)号：US10211103B1

公开(公告)日：2019-02-19

申请号：US15787257

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Dinesh Koli ,  Yuan Zhou ,  Xingzhao Shi ,  Chih-Chiang Chang ,  Tai Fong Chao

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of forming a SAC cap with SiN U-shaped and oxide T-shaped structures and the resulting devices are provided. Embodiments include forming a substrate with a trench and a plurality of gate structures; forming a nitride liner over portions of the substrate and along sidewalls of each gate structure; forming an ILD between each gate structure and in the trench; recessing each gate structure between the ILD; forming a U-shaped nitride liner over each recessed gate structure; forming an a-Si layer over the nitride liner and the U-shaped nitride liner; removing portions of the nitride liner, the U-shaped nitride liner and the a-Si layer; forming a W layer over portions of the substrate adjacent to and between the a-Si layer; forming an oxide liner over the nitride liner, the U-shaped nitride liner and along sidewalls of the W layer; and forming an oxide layer over portions of the oxide liner.

公开(公告)号：US09299584B2

公开(公告)日：2016-03-29

申请号：US14314595

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dinesh Koli ,  Deepasree Konduparthi

IPC: H01L21/4763 ,  H01L21/321 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L21/3212 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.

Abstract translation: 提供了形成集成电路的器件和方法以及具有平坦化永久层的FinFET器件。 在一个实施例中，形成平坦化永久层的方法包括提供具有不平坦表面形貌的基底。 永久层在基底基材上共形地形成。 永久层包括对应于基底基板的表面形貌的凸起部分和下沉部分。 在永久层上共形形成牺牲层。 永久层的牺牲层和凸起部分被化学机械平面化以提供平坦化的永久层。 在化学机械平面化之后基本上完全去除牺牲层。