公开(公告)号：US10055535B2

公开(公告)日：2018-08-21

申请号：US15277796

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Piyush Pathak ,  Robert C. Pack ,  Wei-Long Wang ,  Karthik Krishnamoorthy ,  Fadi S. Batarseh ,  Uwe Paul Schroeder ,  Sriram Madhavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.