公开(公告)号：US10095826B2

公开(公告)日：2018-10-09

申请号：US15184164

申请日：2016-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shikha Somani ,  Sriram Madhavan ,  Thomas Herrmann ,  Stefan Schüler ,  Uwe Schroeder ,  Shobhit Malik ,  Eric Chiu

IPC: G06F17/50

Abstract: A method and apparatus for selecting Si wafer WP based on individual or multiple DFM decks for Si-feed-forward and Si-feed-back analysis are provided. Embodiments include generating markers for a wafer from an individual DFM deck; generating UCF Indexes; determining whether a representative marker corresponding to a UCF is a candidate for WP prediction; extracting markers corresponding to that UCF-Index (UEF data) from a candidate; performing a UCF-Index-based sampling on the extracted UEF data set if a number of markers in the extracted UEF data set is larger than an inspection requirement; adding a location of each marker or group of markers in the extracted UEF data set to a sitelist after the UCF-Index-based sampling; sending the sitelist to a foundry for metrology analysis on sitelist locations; and adding the sitelist locations and corresponding UCF Index and metrology parameters to a design analysis database for analyzing other wafers/UCF Indexes.

公开(公告)号：US10055535B2

公开(公告)日：2018-08-21

申请号：US15277796

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Piyush Pathak ,  Robert C. Pack ,  Wei-Long Wang ,  Karthik Krishnamoorthy ,  Fadi S. Batarseh ,  Uwe Paul Schroeder ,  Sriram Madhavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.

公开(公告)号：US10372871B2

公开(公告)日：2019-08-06

申请号：US15662419

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lynn Tao-Ning Wang ,  Sriram Madhavan

IPC: G06F17/50

Abstract: An IC design layout is decomposed into multiple masks to produce an initial output. A post-decomposition optimization is performed. The post-decomposition optimization includes identifying hotspots in the multiple masks, clustering features that contribute to the hotspots into clusters, identifying ones of the clusters that can be relocated to a different mask to eliminate the hotspot, without violating design rules, as reversible clusters, ranking movement of the reversible clusters by comparing the reversible clusters, as potentially moved, to known manufacturability metrics, and moving the reversible clusters to different masks according to the priority established by the ranking, to produce a post-decomposition optimized tape-out. The IC devices are manufactured by applying the post-decomposition optimized tape-out to manufacturing equipment.

公开(公告)号：US20190034577A1

公开(公告)日：2019-01-31

申请号：US15662419

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lynn Tao-Ning Wang ,  Sriram Madhavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/00 ,  G06F2217/12

Abstract: An IC design layout is decomposed into multiple masks to produce an initial output. A post-decomposition optimization is performed. The post-decomposition optimization includes identifying hotspots in the multiple masks, clustering features that contribute to the hotspots into clusters, identifying ones of the clusters that can be relocated to a different mask to eliminate the hotspot, without violating design rules, as reversible clusters, ranking movement of the reversible clusters by comparing the reversible clusters, as potentially moved, to known manufacturability metrics, and moving the reversible clusters to different masks according to the priority established by the ranking, to produce a post-decomposition optimized tape-out. The IC devices are manufactured by applying the post-decomposition optimized tape-out to manufacturing equipment.