公开(公告)号：US20170373024A1

公开(公告)日：2017-12-28

申请号：US15195029

申请日：2016-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Ezra D.B. Hall ,  Faraydon Pakbaz ,  Sebastian T. Ventrone

IPC: H01L23/00 ,  G01R31/28 ,  H01L23/495

CPC classification number: H01L23/573 ,  G01R31/2853 ,  G01R31/2896 ,  G01R31/44 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.