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    Transition once multiplexer circuit
    1.
    发明授权
    Transition once multiplexer circuit 有权

    公开(公告)号：US10788877B1

    公开(公告)日：2020-09-29

    申请号：US16787520

    申请日：2020-02-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sebastian T. Ventrone ,  Lansing D. Pickup

    IPC: G06F1/32 ,  H03K3/037 ,  H03K17/00 ,  G06F1/04

    Abstract: Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.

    INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION
    4.
    发明申请
    INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION 审中-公开
    集成电路时序可变性降低

    公开(公告)号：US20160117433A1

    公开(公告)日：2016-04-28

    申请号：US14525320

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric A. Foreman ,  Chaitanya Kompalli ,  Sudeep Mandal ,  Sebastian T. Ventrone

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/84

    Abstract: As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.

    Abstract translation: 如本文所公开的，由计算机执行的用于集成电路定时可变性降低的方法包括加载对应于芯片设计的网表，其中芯片设计包括一个或多个电路和多个后填充特征，遍历部分 所述网表对应于电路，从多个后填充特征确定所述电路的填充后环境，以及基于所述填充后环境对所述电路的定时方差进行建模。 该方法还可以包括改变一个或多个后填充特征以实现目标延迟。 该方法可以包括生成电路定时和定时方差的报告。 可以同时遍历一个或多个电路。 定时方差可以用标准时间方差的缩放因子来建模。 本文还公开了与该方法对应的计算机系统和计算机程序产品。

    ENABLING OF FUNCTIONAL LOGIC IN IC USING THERMAL SEQUENCE ENABLING TEST
    5.
    发明申请
    ENABLING OF FUNCTIONAL LOGIC IN IC USING THERMAL SEQUENCE ENABLING TEST 有权

    公开(公告)号：US20210033660A1

    公开(公告)日：2021-02-04

    申请号：US16527146

    申请日：2019-07-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sebastian T. Ventrone ,  Richard S. Graf ,  Ezra D. B. Hall ,  Jack R. Smith

    IPC: G01R31/28 ,  H04L9/32

    Abstract: An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

    IC WAFER FOR IDENTIFICATION OF CIRCUIT DIES AFTER DICING
    6.
    发明申请
    IC WAFER FOR IDENTIFICATION OF CIRCUIT DIES AFTER DICING 审中-公开

    公开(公告)号：US20190214348A1

    公开(公告)日：2019-07-11

    申请号：US15867118

    申请日：2018-01-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

    IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66

    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

    PROCESSOR WITH CONTENT ADDRESSABLE MEMORY (CAM) AND MONITOR COMPONENT
    7.
    发明申请
    PROCESSOR WITH CONTENT ADDRESSABLE MEMORY (CAM) AND MONITOR COMPONENT 审中-公开

    公开(公告)号：US20170255471A1

    公开(公告)日：2017-09-07

    申请号：US15062302

    申请日：2016-03-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jack R. Smith ,  Sebastian T. Ventrone ,  Ezra D. B. Hall

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F3/06

    CPC classification number: G06F9/3832 ,  G06F9/3808

    Abstract: Various embodiments include processors for processing operations. In some cases, a processor includes: an instruction fetch component configured to fetch processing instructions; an instruction cache component connected with the instruction fetch component, configured to store the processing instructions; an execution component connected with the instruction cache component, configured to execute the processing instructions; a monitor component connected with the execution component, configured to receive execution results from the processing instructions; and a content addressable memory (CAM) component connected with the instruction fetch component and the monitor component, wherein the monitor component stores a portion of the execution results in the CAM for subsequent use in bypassing the execution component.

    Sensing circuits for charge trap transistors
    8.
    发明授权
    Sensing circuits for charge trap transistors 有权

    公开(公告)号：US11101010B2

    公开(公告)日：2021-08-24

    申请号：US16568394

    申请日：2019-09-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  Sebastian T. Ventrone ,  James A. Svarczkopf ,  Igor Arsovski

    IPC: G11C17/18 ,  G11C7/06 ,  G11C7/08 ,  G11C11/409

    Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

    Stacked dies using one or more interposers
    9.
    发明授权
    Stacked dies using one or more interposers 有权

    公开(公告)号：US10249590B2

    公开(公告)日：2019-04-02

    申请号：US15614850

    申请日：2017-06-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Sebastian T. Ventrone ,  Richard S. Graf

    IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L25/065

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

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