公开(公告)号：US09240324B2

公开(公告)日：2016-01-19

申请号：US14328921

申请日：2014-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

IPC: H01L21/28 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L21/28008 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract translation: 一种防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括沉积和蚀刻栅极材料以部分地填充柱之间的空间并形成用于存储单元的字线，蚀刻一对柱之间的字线的栅极接触区域，形成电绝缘材料的间隔物 所述栅极接触区域以及在所述一对柱之间沉积栅极接触以与所述栅极材料电接触，使得所述间隔物围绕所述栅极接触。

公开(公告)号：US09209086B2

公开(公告)日：2015-12-08

申请号：US13947316

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract translation: 提供了在替代浇口装置工艺流程中集成低温自对准硅化物形成技术。 一方面，提供了一种制造FET器件的方法，包括以下步骤。 在晶片的有效区域上形成虚拟栅极。 间隙填充材料沉积在虚拟栅极周围。 虚拟栅极被选择性地移除到间隙填充材料上，在间隙填充材料中形成沟槽。 在间隙填充材料的沟槽中形成替换栅极。 更换浇口凹陷在间隙填充材料的表面下方。 在替换门上方的凹槽中形成栅极盖。 间隙填充材料被回蚀以暴露该器件的源极和漏极区域的至少一部分。 在设备的源极和漏极区域上形成自对准硅化物。