公开(公告)号：US20160035743A1

公开(公告)日：2016-02-04

申请号：US14866878

申请日：2015-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L27/12 ,  H01L29/417 ,  H01L25/065 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L25/065 ,  H01L27/092 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

公开(公告)号：US09281397B2

公开(公告)日：2016-03-08

申请号：US14158539

申请日：2014-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract translation: 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US09209086B2

公开(公告)日：2015-12-08

申请号：US13947316

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract translation: 提供了在替代浇口装置工艺流程中集成低温自对准硅化物形成技术。 一方面，提供了一种制造FET器件的方法，包括以下步骤。 在晶片的有效区域上形成虚拟栅极。 间隙填充材料沉积在虚拟栅极周围。 虚拟栅极被选择性地移除到间隙填充材料上，在间隙填充材料中形成沟槽。 在间隙填充材料的沟槽中形成替换栅极。 更换浇口凹陷在间隙填充材料的表面下方。 在替换门上方的凹槽中形成栅极盖。 间隙填充材料被回蚀以暴露该器件的源极和漏极区域的至少一部分。 在设备的源极和漏极区域上形成自对准硅化物。

公开(公告)号：US09548238B2

公开(公告)日：2017-01-17

申请号：US13964286

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract translation: 一种半导体器件的制造方法，包括在基板上的多个栅极上形成有机平坦化层，其中，所述多个栅极各自包括间隔层，在所述有机平坦化层上形成氧化物层， 氧化层以暴露有机平坦化层，剥离有机平坦化层以形成空腔，在空腔中的至少一个栅极上图案化直接可光刻图案化的间隙电介质，以及在空腔的剩余部分中沉积导电接触 。

公开(公告)号：US09385122B2

公开(公告)日：2016-07-05

申请号：US14686260

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-Lin Cheng ,  Jack Oon Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/267 ,  H01L29/165

CPC classification number: H01L27/088 ,  H01L21/02647 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

公开(公告)号：US09240326B2

公开(公告)日：2016-01-19

申请号：US14028022

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-bang Yau

IPC: H01L29/76 ,  H01L29/40 ,  H01L23/48 ,  H01L21/283 ,  H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/283 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/785

Abstract: A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.