公开(公告)号：US20130307090A1

公开(公告)日：2013-11-21

申请号：US13948672

申请日：2013-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Thorsten Kammler ,  Gunda Beernink ,  Carsten Reichel

IPC: H01L29/161

CPC classification number: H01L29/161 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.

Abstract translation: 可以通过在晶体管的沟道区域中提供特别设计的半导体合金来调整复杂晶体管的阈值电压，其中该半导体材料相对于在沟道区域中诱导应变分量的负面影响可以被减小或过量， 通过另外结合应变调节物种来补偿。 例如，可以在沟道区域中引入碳物质，其阈值电压可以基于P沟道晶体管的硅/锗合金来调节。 因此，可以在早期制造阶段形成复杂的金属栅电极。

公开(公告)号：US20160071978A1

公开(公告)日：2016-03-10

申请号：US14944833

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Abstract translation: 半导体器件包括位于晶体管的有源区域中的漏极和源极区域以及横向设置在漏极和源极区域之间的沟道区域，该沟道区域包括位于半导体基底材料上的半导体基底材料和阈值电压调节半导体材料。 门极电极结构位于阈值电压调节用半导体材料上，并且包含位于第一半导体材料上方的第一半导体材料和第二半导体材料的应变诱发半导体合金嵌入有源区的半导体基底材料中。 第三半导体材料的结晶缓冲层包围嵌入式应变诱导半导体合金，其中结晶缓冲层的上部横向限制包括阈值电压调节半导体材料的侧壁的沟道区，并且位于第二半导体材料 和阈值电压调节半导体材料。

公开(公告)号：US09484459B2

公开(公告)日：2016-11-01

申请号：US14944833

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L27/10 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Abstract translation: 半导体器件包括位于晶体管的有源区域中的漏极和源极区域以及横向设置在漏极和源极区域之间的沟道区域，该沟道区域包括位于半导体基底材料上的半导体基底材料和阈值电压调节半导体材料。 门极电极结构位于阈值电压调节用半导体材料上，并且包含位于第一半导体材料上方的第一半导体材料和第二半导体材料的应变诱发半导体合金嵌入有源区的半导体基底材料中。 第三半导体材料的结晶缓冲层包围嵌入式应变诱导半导体合金，其中结晶缓冲层的上部横向限制包括阈值电压调节半导体材料的侧壁的沟道区，并且位于第二半导体材料 和阈值电压调节半导体材料。