公开(公告)号：US10141229B2

公开(公告)日：2018-11-27

申请号：US15279559

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jürgen Faul ,  Thorsten Kammler

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8234

Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

公开(公告)号：US08674416B2

公开(公告)日：2014-03-18

申请号：US13663589

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Reichel ,  Thorsten Kammler ,  Annekathrin Zeun ,  Stephan Kronholz

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823481 ,  H01L27/092

Abstract: Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material.

Abstract translation: 通常，本文公开的主题涉及具有阈值可变性降低的半导体器件，其具有在器件有源区域中的阈值调节半导体材料。 本文公开的一个说明性的半导体器件包括在半导体器件衬底的半导体层中的有源区，该有源区具有由隔离结构横向描绘的区域长度和区域宽度。 所述半导体器件还包括阈值调节半导体合金材料层，所述阈值调节半导体合金材料层基本上不与所述隔离结构重叠地位于所述有源区上，所述阈值调节半导体合金材料层具有小于所述区域长度的层长度。 此外，所公开的半导体器件包括位于阈值调节半导体合金材料层上方的栅电极结构，该栅电极结构包括形成在高k电介质材料上方的高k电介质材料和含金属电极材料。

公开(公告)号：US20130307090A1

公开(公告)日：2013-11-21

申请号：US13948672

申请日：2013-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Thorsten Kammler ,  Gunda Beernink ,  Carsten Reichel

IPC: H01L29/161

CPC classification number: H01L29/161 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.

Abstract translation: 可以通过在晶体管的沟道区域中提供特别设计的半导体合金来调整复杂晶体管的阈值电压，其中该半导体材料相对于在沟道区域中诱导应变分量的负面影响可以被减小或过量， 通过另外结合应变调节物种来补偿。 例如，可以在沟道区域中引入碳物质，其阈值电压可以基于P沟道晶体管的硅/锗合金来调节。 因此，可以在早期制造阶段形成复杂的金属栅电极。

公开(公告)号：US20180090386A1

公开(公告)日：2018-03-29

申请号：US15279559

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jürgen Faul ,  Thorsten Kammler

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L21/823807 ,  H01L21/28255 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/78687

Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

公开(公告)号：US20160247891A1

公开(公告)日：2016-08-25

申请号：US14628947

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC: H01L29/49 ,  H01L23/535 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract translation: 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。

公开(公告)号：US09466685B2

公开(公告)日：2016-10-11

申请号：US14628947

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract translation: 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。

公开(公告)号：US20190051565A1

公开(公告)日：2019-02-14

申请号：US15673519

申请日：2017-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees ,  Thorsten Kammler

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor (CMOS) device comprising an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region is provided, that comprises: depositing a raised source and drain (RSD) layer of a first type in the NMOS region and the PMOS region at the same time; selectively removing the RSD layer of the first type in one of the NMOS region and the PMOS region; and depositing an RSD layer of a second type in the one of the NMOS region and the PMOS region.

公开(公告)号：US09876111B2

公开(公告)日：2018-01-23

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20170170317A1

公开(公告)日：2017-06-15

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US09514942B1

公开(公告)日：2016-12-06

申请号：US15060009

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Thorsten Kammler ,  Andreas Hellmich ,  Carsten Grass

IPC: H01L21/28 ,  H01L21/66 ,  H01L21/311 ,  H01L21/32 ,  H01L27/12

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L22/26 ,  H01L27/1207

Abstract: A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Abstract translation: 公开了一种在具有体积区域和SOI区域的形貌的混合衬底结构上形成栅极结构的方法，包括在SOI和体区上形成栅极材料层，在栅极材料层上方形成掩模层，形成第一 在所述掩模层上方形成平坦化层，在所述第一平坦化层上方形成第一栅极结构掩模图案，使与所述第一栅极结构掩模图案对准的所述第一平坦化图案图案化，以及根据所述图案化的第一平坦化层图案化所述掩模层， 在栅极掩模上设置在栅极材料层上方。