公开(公告)号：US09349864B1

公开(公告)日：2016-05-24

申请号：US14826477

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Timothy James Mcardle ,  Judson Robert Holt ,  Churamani Gaire

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2254 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods for fabricating integrated circuits including selectively forming layers of increased dopant concentration are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a material layer with a selected facet on a selected plane and a non-selected facet on a non-selected plane. The method further includes performing an epitaxial deposition process with a dopant source to grow an in-situ doped epitaxial material on the material layer. The epitaxial deposition process grows the in-situ doped epitaxial material on the selected facet at a first growth rate and over the non-selected facet at a second growth rate greater than the first growth rate. A layer of increased dopant concentration is selectively formed over the selected facet.

Abstract translation: 提供了包括选择性地形成增加的掺杂剂浓度的层的集成电路的制造方法。 在一个实施例中，用于制造集成电路的方法包括在未选择的平面上在所选择的平面上形成具有选定面的材料层和未选择的面。 该方法还包括用掺杂剂源执行外延沉积工艺以在材料层上生长原位掺杂的外延材料。 外延沉积工艺以选择的小平面上的原位掺杂外延材料以第一生长速率和非选择的平面以大于第一生长速率的第二生长速率生长。 在选定的刻面上选择性地形成增加掺杂剂浓度的层。

公开(公告)号：US10043893B1

公开(公告)日：2018-08-07

申请号：US15668012

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US20180130656A1

公开(公告)日：2018-05-10

申请号：US15843649

申请日：2017-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson Robert Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James Mcardle ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US20200328306A1

公开(公告)日：2020-10-15

申请号：US16382184

申请日：2019-04-11

Applicant: GlobalFoundries Inc.

Inventor： Jin Wallner ,  Heng Yang ,  Judson Robert Holt

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.

公开(公告)号：US10163635B1

公开(公告)日：2018-12-25

申请号：US15797794

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Judson Robert Holt

IPC: H01L21/033 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/861 ,  H01L29/78 ,  H01L49/02

Abstract: A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.

公开(公告)号：US10326007B2

公开(公告)日：2019-06-18

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.