公开(公告)号：US20170018463A1

公开(公告)日：2017-01-19

申请号：US14800970

申请日：2015-07-16

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract translation: 晶体管器件包括衬底; 形成在所述基板上的源极区域和漏极区域; 以及与所述源极区域和所述漏极区域中的至少一个接触形成的源极/漏极接触部，所述源极/漏极接触部包括导电金属和设置在所述导电金属与所述源极和漏极区域中的至少一个之间的双层 包括与导电金属接触的金属氧化物层的双层以及与源区和漏区中的至少一个接触的二氧化硅层。

公开(公告)号：US10056469B1

公开(公告)日：2018-08-21

申请号：US15430647

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui-feng Li ,  Laertis Economikos

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/02

Abstract: A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.

公开(公告)号：US09589851B2

公开(公告)日：2017-03-07

申请号：US14800970

申请日：2015-07-16

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/532 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/535

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract translation: 晶体管器件包括衬底; 形成在所述基板上的源极区域和漏极区域; 以及与所述源极区域和所述漏极区域中的至少一个接触形成的源极/漏极接触部，所述源极/漏极接触部包括导电金属和设置在所述导电金属与所述源极和漏极区域中的至少一个之间的双层 包括与导电金属接触的金属氧化物层的双层以及与源区和漏区中的至少一个接触的二氧化硅层。

公开(公告)号：US10153201B2

公开(公告)日：2018-12-11

申请号：US15417848

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/485 ,  H01L29/08 ,  H01L27/092

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

公开(公告)号：US20170133265A1

公开(公告)日：2017-05-11

申请号：US15417848

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.