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    Dual metal-insulator-semiconductor contact structure and formulation method
    6.
    发明授权
    Dual metal-insulator-semiconductor contact structure and formulation method 有权

    公开(公告)号：US10535606B2

    公开(公告)日：2020-01-14

    申请号：US16040752

    申请日：2018-07-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

    发明人： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

    IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L29/66

    摘要： A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

    Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
    7.
    发明授权
    Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions 有权

    公开(公告)号：US10396000B2

    公开(公告)日：2019-08-27

    申请号：US14789476

    申请日：2015-07-01

    申请人： International Business Machines Corporation ,  Globalfoundries, Inc.

    发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

    IPC分类号： H01L21/66 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

    摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

    Width adjustment of stacked nanowires
    10.
    发明授权
    Width adjustment of stacked nanowires 有权

    公开(公告)号：US10069015B2

    公开(公告)日：2018-09-04

    申请号：US15276372

    申请日：2016-09-26

    申请人： International Business Machines Corporation ,  Globalfoundries Inc.

    发明人： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

    IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

    摘要： In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.