公开(公告)号：US10262941B2

公开(公告)日：2019-04-16

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Tuhin Guha Neogi ,  Kai Sun ,  Deniz Elizabeth Civay ,  David Charles Pritchard ,  Andy Wei

IPC: H01L21/33 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20190392106A1

公开(公告)日：2019-12-26

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F17/50 ,  G03F1/36

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

公开(公告)号：US10796056B2

公开(公告)日：2020-10-06

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F30/00 ,  G06F30/392 ,  G03F1/36 ,  G06F30/398 ,  H01L21/78 ,  G06F111/04 ,  G06F111/20

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.