公开(公告)号：US09786545B1

公开(公告)日：2017-10-10

申请号：US15271519

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Byoung Youp Kim ,  Craig Michael Child, Jr. ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/0251

Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.

公开(公告)号：US20170263506A1

公开(公告)日：2017-09-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L21/768 ,  G06F17/50 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US20160300754A1

公开(公告)日：2016-10-13

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针迹。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US08969199B1

公开(公告)日：2015-03-03

申请号：US14054251

申请日：2013-10-15

Applicant: Globalfoundries Inc.

Inventor： Lei Yuan ,  Jason Eugene Stephens ,  Li Yang ,  Soo Han Choi

IPC: H01L21/312 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0334 ,  H01L21/31144 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11859

Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括使用三种图案化的光致抗蚀剂蚀刻掩模图案化硬掩模层，其中对应于交叉耦合栅极接触结构的一部分但不是全部的第一特征存在于第一 三个图案化的光致抗蚀剂蚀刻掩模和对应于交叉耦合栅极接触结构的一部分但不是全部的第二特征存在于三个图案化的光致抗蚀剂蚀刻掩模的第二或第三个中，使用 图案化的硬掩模层作为蚀刻掩模，并且在绝缘材料层中的沟槽中形成交叉耦合栅极接触结构。

公开(公告)号：US10236350B2

公开(公告)日：2019-03-19

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/768

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US09465907B2

公开(公告)日：2016-10-11

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20160026748A1

公开(公告)日：2016-01-28

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案，将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20150357120A1

公开(公告)日：2015-12-10

申请号：US14298040

申请日：2014-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick Alan Augur ,  Jason Eugene Stephens

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/06

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/01 ,  H01G4/06 ,  H01G4/232 ,  H01G4/385 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract translation: 电容器结构包括第一金属层，第一金属层包括在第一多个水平间隔的高压导电线之间水平定位的第一多个水平间隔的中性导电线。 电容器结构还包括第二金属层，第二金属层包括位于第二多个水平间隔的高压导电线之间水平定位的第二多个水平间隔的中性导电线。 所述电容器结构还包括位于所述第一金属层的垂直下方且位于所述第二金属层的上方的第三金属层，所述第三金属层包括第三多个水平间隔的中性导电线，其水平位于第一多个水平间隔的低电压 导线。 第一组多个低压线路垂直地定位在第一和第二多个中性线之间。

公开(公告)号：US20180033701A1

公开(公告)日：2018-02-01

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L23/535 ,  H01L21/027 ,  G06F17/50 ,  H01L21/768 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8234

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09852986B1

公开(公告)日：2017-12-26

申请号：US15362035

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche

IPC: H01L21/308 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/76843 ,  H01L21/76892

Abstract: A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is patterned into the mandrel layer. Mandrel spacers are formed self-aligned on sidewalls of the mandrels. A gapfill layer is disposed and planarized over the semiconductor structure. Non-mandrel pillars are formed over the planarized gapfill layer. Exposed portions of the gapfill layer are etched to form non-mandrel plugs preserved by the pillars. The pillars are removed to form a pattern, the pattern including the non-mandrel plugs. The pattern is utilized to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack. The array includes non-mandrel dielectric structures formed from the non-mandrel plugs.