公开(公告)号：US09589850B1

公开(公告)日：2017-03-07

申请号：US14964746

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Kisup Chung ,  Sivananda Kanakasabapathy

IPC: H01L21/8238 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/823456 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/4966

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed. Embodiments include providing a dielectric layer over first-type and second-type transistor regions, and long and short channel-cavities in the dielectric in each transistor region; conformally forming a gate dielectric layer in the long and short channel-cavities, and on an upper surface of the dielectric; conformally forming a first-type work-function metal layer on the gate dielectric; forming a block-mask over the first-type transistor region; removing the first-type work-function metal from the second-type transistor region; removing the block-mask; conformally forming a second-type work-function metal on all exposed surfaces; forming a metal barrier layer on exposed surfaces and filling the short channel-cavities; filling the long channel-cavities with a conductive material; planarizing all layers down to the upper surface of the dielectric; and applying a tilted ion beam to recess the gate dielectric, first and second type work-function metal, and metal barrier layers.

Abstract translation: 公开了空腔和结果装置中材料的受控凹陷。 实施例包括在第一类型和第二类型晶体管区域上提供介电层，以及在每个晶体管区域中的电介质中的长和短沟道腔; 在长和短通道腔中保形地形成栅极电介质层，并在电介质的上表面上形成栅介电层; 在栅极电介质上保形地形成第一型功函数金属层; 在所述第一型晶体管区域上形成块掩模; 从第二类型晶体管区域去除第一类型功函数金属; 去除阻挡掩模; 在所有暴露的表面上保形地形成第二种功能金属; 在暴露的表面上形成金属阻挡层并填充短沟槽; 用导电材料填充长通道腔; 将所有层平坦化到电介质的上表面; 并且施加倾斜的离子束以使所述栅极电介质，第一和第二类型功函数金属以及金属阻挡层凹陷。

公开(公告)号：US20180277652A1

公开(公告)日：2018-09-27

申请号：US15468170

申请日：2017-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kisup Chung ,  Victor Chan ,  Koji Watanabe

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966

Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).

公开(公告)号：US10217839B2

公开(公告)日：2019-02-26

申请号：US15468170

申请日：2017-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kisup Chung ,  Victor Chan ,  Koji Watanabe

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

Abstract: Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.