公开(公告)号：US20190131432A1

公开(公告)日：2019-05-02

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, JR. ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.