公开(公告)号：US20190131432A1

公开(公告)日：2019-05-02

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, JR. ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US20140187028A1

公开(公告)日：2014-07-03

申请号：US13732455

申请日：2013-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

公开(公告)号：US20190027556A1

公开(公告)日：2019-01-24

申请号：US15656574

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Rishikesh Krishnan ,  Jinping Liu ,  Yiheng Xu ,  Joseph F. Shepard, JR.

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105

Abstract: A method of forming a shallow trench isolation (STI) for an integrated circuit (IC) structure to mitigate fin bending disclosed. The method may include forming a first insulator layer in a first portion of an opening in a substrate by a bottom-up atomic layer deposition (ALD) process; and forming a second insulator layer on the first insulator layer in a second portion of the opening. The opening may be position between a set of fins in the substrate. The method may further include forming an oxide liner in the opening before the forming the first insulator layer. The second insulator layer may be formed by deposition using a flowable chemical vapor deposition (FCVD) process, high aspect ratio process (HARP), high-density plasma chemical vapor deposition (HDP CVD) process, or any other conventional insulator material deposition process.

公开(公告)号：US20170294519A1

公开(公告)日：2017-10-12

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, JR.

IPC: H01L29/423 ,  H01L21/027 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

公开(公告)号：US20160240478A1

公开(公告)日：2016-08-18

申请号：US14623115

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer ,  Kriteshwar K. Kohli ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Keith Kwong Hon Wong

IPC: H01L23/525 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/5228 ,  H01L27/11206

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Abstract translation: 用于形成使用钨硅的精密电阻器或e熔丝结构的方法。 通过将氮注入结构来改变钨硅层。