公开(公告)号：US09696376B2

公开(公告)日：2017-07-04

申请号：US14645541

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo Mikalo

IPC: G01R31/30 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R31/3008 ,  G01R31/025 ,  G01R31/2851

Abstract: A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit is provided including a logarithmic transducer electrically connected to the DUT and a voltmeter electrically connected to the logarithmic transducer.

公开(公告)号：US09368506B2

公开(公告)日：2016-06-14

申请号：US14741528

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Stefan Flachowsky

IPC: G11C11/34 ,  H01L27/115 ,  G11C16/04 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US10048311B2

公开(公告)日：2018-08-14

申请号：US14848804

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo Mikalo

IPC: G01R31/02 ,  G01R31/26 ,  H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  G01R31/28

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

公开(公告)号：US09257353B1

公开(公告)日：2016-02-09

申请号：US14523266

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Uwe Dersch

IPC: H01L27/00 ,  H01L21/66 ,  H01L29/861 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L22/34 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0676 ,  H01L29/8613

Abstract: Integrated circuits that include bi-directional protection diode structures are disclosed. In one example, an integrated circuit includes a test circuit portion for testing the functionality of the integrated circuit during or after fabrication of the integrated circuit. The test circuit portion includes first, second, and third diode structures and a resistor structure. The first and third diode structures are in parallel with one another and in series with the resistor, and the resistor and the first and third diode structures are in series with the second diode structure. The first and third diode structures are configured for current flow in a first direction and the second diode structure is configured for current flow in a second direction that is opposite the first direction.

Abstract translation: 公开了包括双向保护二极管结构的集成电路。 在一个示例中，集成电路包括用于在集成电路制造期间或之后测试集成电路的功能的测试电路部分。 测试电路部分包括第一，第二和第三二极管结构和电阻器结构。 第一和第三二极管结构彼此并联并且与电阻器串联，并且电阻器和第一和第三二极管结构与第二二极管结构串联。 第一和第三二极管结构被配置为在第一方向上的电流流动，并且第二二极管结构被配置为在与第一方向相反的第二方向上的电流流动。

公开(公告)号：US20150333080A1

公开(公告)日：2015-11-19

申请号：US14741528

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。