公开(公告)号：US09076688B1

公开(公告)日：2015-07-07

申请号：US14202675

申请日：2014-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Lutz ,  Robert Melzer

IPC: H01L21/66

CPC classification number: H01L22/12 ,  G01B2210/56 ,  H01L22/30

Abstract: Methodologies and an apparatus for enabling scatterometry to be used to estimate dimensions of fabricated semiconductor devices are provided. Embodiments include initiating scatterometry on a fabricated test structure comprising a two-dimensional array of features, each of the features being horizontally separated from an adjacent one of the features by a narrow trench region extending a first distance in a horizontal direction and each of the features being vertically separated from an adjacent one of the features by an isolated trench region extending a second distance in a vertical direction. A scattering spectra corresponding to one or more physical characteristics of the fabricated test structure based on results of the scatterometry is determined. The scattering spectra is associated with the one or more physical characteristics in a library for estimating at least one physical dimension of a fabricated structure.

Abstract translation: 提供了用于使散射仪用于估计制造的半导体器件的尺寸的方法和装置。 实施例包括在包括特征的二维阵列的制造的测试结构上启动散射测量，每个特征通过在水平方向上延伸第一距离的窄沟槽区域与相邻特征之间水平分离，并且每个特征 通过在垂直方向上延伸第二距离的隔离沟槽区域与相邻的一个特征垂直分离。 确定对应于基于散射测量结果的制造的测试结构的一个或多个物理特性的散射光谱。 散射光谱与文库中用于估计制造结构的至少一个物理尺寸的一个或多个物理特性相关联。

公开(公告)号：US09177874B2

公开(公告)日：2015-11-03

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成光学平坦化层（OPL），在所述第一区域中的所述OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US20150064812A1

公开(公告)日：2015-03-05

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。