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    Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
    1.
    发明授权
    Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer 有权
    在晶体管的源极/漏极区之上形成硅/锗保护层的方法和具有这种保护层的器件

    公开(公告)号：US09029919B2

    公开(公告)日：2015-05-12

    申请号：US13757205

    申请日：2013-02-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stephan Kronholz ,  Joachim Patzer

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    Abstract: Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

    Abstract translation: 这里公开了在晶体管的源极/漏极区之上形成硅/锗保护层的各种方法。 本文公开的一种方法包括在靠近栅极结构的衬底中形成多个凹槽，在凹槽中形成半导体材料，在半导体材料上形成至少一层硅，并在层上形成由硅锗组成的覆盖层 的硅。 本文公开的一种装置包括位于衬底上方的栅极结构，在栅极结构附近形成在衬底中的多个凹槽，至少部分地位于凹部中的至少一层半导体材料，位于至少至少 一层半导体材料，以及由位于硅层上的硅/锗组成的覆盖层。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS
    2.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS 有权
    形成含硅和非电解电路元件的半导体结构的方法

    公开(公告)号：US20150031179A1

    公开(公告)日：2015-01-29

    申请号：US14293627

    申请日：2014-06-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Dominic Thurmer ,  Sven Metzger ,  Joachim Patzer ,  Markus Lenski

    IPC: H01L21/283 ,  H01L29/66

    CPC classification number: H01L21/283 ,  H01L21/268 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7847

    Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

    Abstract translation: 一种方法包括提供包括至少一个包括第一半导体材料的第一电路元件和包括第二半导体材料的至少一个第二电路元件的半导体结构。 形成具有固有应力的电介质层，其包括至少一个第一电路元件上的第一部分和至少一个第二电路元件上的第二部分。 进行第一退火处理，其中通过应力记忆至少在第一半导体材料中产生固有应力，然后去除电介质层的第一部分。 形成金属层，进行第二退火处理，其中金属和第一半导体材料通过化学反应形成硅化物。 电介质层的第二部分基本上防止了第二半导体材料与金属之间的化学反应。

    BALANCING ASYMMETRIC SPACERS
    3.
    发明申请
    BALANCING ASYMMETRIC SPACERS 有权
    平衡不对称间距

    公开(公告)号：US20150187660A1

    公开(公告)日：2015-07-02

    申请号：US14143362

    申请日：2013-12-30

    Applicant: Globalfoundries Inc.

    Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

    IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/311 ,  H01L21/285

    CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

    Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

    Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同的掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。

    METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER
    4.
    发明申请
    METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER 有权
    形成硅/锗保护层的方法在晶体管的源极/漏极区域和具有这种保护层的器件

    公开(公告)号：US20140217480A1

    公开(公告)日：2014-08-07

    申请号：US13757205

    申请日：2013-02-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Stephan Kronholz ,  Joachim Patzer

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    Abstract: Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

    Abstract translation: 这里公开了在晶体管的源极/漏极区之上形成硅/锗保护层的各种方法。 本文公开的一种方法包括在靠近栅极结构的衬底中形成多个凹槽，在凹槽中形成半导体材料，在半导体材料上形成至少一层硅，并在层上形成由硅锗组成的覆盖层 的硅。 本文公开的一种装置包括位于衬底上方的栅极结构，在栅极结构附近形成在衬底中的多个凹槽，至少部分地位于凹部中的至少一层半导体材料，位于至少至少 一层半导体材料，以及由位于硅层上的硅/锗组成的覆盖层。

    Integrated circuits with protected resistors and methods for fabricating the same
    6.
    发明授权
    Integrated circuits with protected resistors and methods for fabricating the same 有权
    具有受保护电阻的集成电路及其制造方法

    公开(公告)号：US09111756B2

    公开(公告)日：2015-08-18

    申请号：US14033789

    申请日：2013-09-23

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Joachim Patzer ,  Hans-Peter Moll

    IPC: H01L21/44 ,  H01L21/033 ,  H01L21/768

    CPC classification number: H01L21/0332 ,  H01L21/28512 ,  H01L21/76886 ,  H01L27/0629 ,  H01L28/20

    Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

    Abstract translation: 为具有晶体管和电阻器的集成电路提供了方法和装置。 该方法包括在晶体管和电阻器之上沉积第一介电层，随后是非晶硅层。 将非晶硅层注入电阻器上以产生蚀刻掩模，并且在晶体管上去除非晶硅层和第一介电层。 然后将晶体管上的接触位置硅化。

    METHODS OF FORMING ASYMMETRIC SPACERS ON VARIOUS STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
    8.
    发明申请
    METHODS OF FORMING ASYMMETRIC SPACERS ON VARIOUS STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS 有权
    在集成电路产品上形成不同结构的不对称间隔的方法

    公开(公告)号：US20140248778A1

    公开(公告)日：2014-09-04

    申请号：US13781874

    申请日：2013-03-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hans-Peter Moll ,  Joachim Patzer

    IPC: H01L21/02

    CPC classification number: H01L21/02107 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66659

    Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

    Abstract translation: 本文公开的一种示例性方法包括在半导体衬底上形成结构，执行保形沉积工艺以在结构上方形成未掺杂的间隔物材料层，执行成角度的离子注入工艺以在未掺杂的层中形成掺杂间隔物材料的区域 间隔材料，同时留下未掺杂的未掺杂的间隔物材料层的其它部分，并且在执行成角度离子注入工艺之后，执行至少一个蚀刻工艺，其去除未掺杂间隔物材料层的未掺杂部分，从而导致侧壁间隔物 包括位于该结构的至少一侧但不是全部侧面的掺杂间隔物材料。

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