公开(公告)号：US09761689B2

公开(公告)日：2017-09-12

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

公开(公告)号：US09184260B2

公开(公告)日：2015-11-10

申请号：US14080558

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

IPC: H01L21/425 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

公开(公告)号：US09034746B2

公开(公告)日：2015-05-19

申请号：US14524023

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/324 ,  H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅极的暴露的上部。

公开(公告)号：US20150044861A1

公开(公告)日：2015-02-12

申请号：US14524023

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L21/324 ,  H01L29/49 ,  H01L21/3205

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

公开(公告)号：US09368513B2

公开(公告)日：2016-06-14

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。

公开(公告)号：US20150132914A1

公开(公告)日：2015-05-14

申请号：US14080558

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

公开(公告)号：US20150031179A1

公开(公告)日：2015-01-29

申请号：US14293627

申请日：2014-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Sven Metzger ,  Joachim Patzer ,  Markus Lenski

IPC: H01L21/283 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/268 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7847

Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

Abstract translation: 一种方法包括提供包括至少一个包括第一半导体材料的第一电路元件和包括第二半导体材料的至少一个第二电路元件的半导体结构。 形成具有固有应力的电介质层，其包括至少一个第一电路元件上的第一部分和至少一个第二电路元件上的第二部分。 进行第一退火处理，其中通过应力记忆至少在第一半导体材料中产生固有应力，然后去除电介质层的第一部分。 形成金属层，进行第二退火处理，其中金属和第一半导体材料通过化学反应形成硅化物。 电介质层的第二部分基本上防止了第二半导体材料与金属之间的化学反应。

公开(公告)号：US09646838B2

公开(公告)日：2017-05-09

申请号：US14293627

申请日：2014-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Sven Metzger ,  Joachim Patzer ,  Markus Lenski

IPC: H01L21/8234 ,  H01L21/283 ,  H01L27/06 ,  H01L21/268 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L21/285

CPC classification number: H01L21/283 ,  H01L21/268 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7847

Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

公开(公告)号：US20160079086A1

公开(公告)日：2016-03-17

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/3213 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract translation: 本公开提供了一种形成半导体器件的方法，包括半导体器件的栅极结构的成形，使得避免了形成硅化物之后的间隔物去除并且抑制了硅化物突出。 在本公开的一些方面，提供一种形成半导体器件的方法，其中栅极结构设置在半导体衬底的有源区上方，栅极结构包括栅电极材料和侧壁间隔物。 通过对栅极结构施加成形工艺来形成栅电极材料和侧壁间隔物中的至少一个，并且在成形栅极结构上形成硅化物部分。

公开(公告)号：US20160071886A1

公开(公告)日：2016-03-10

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。