公开(公告)号：US08815674B1

公开(公告)日：2014-08-26

申请号：US14172135

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

公开(公告)号：US20150187660A1

公开(公告)日：2015-07-02

申请号：US14143362

申请日：2013-12-30

Applicant: Globalfoundries Inc.

Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同的掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。

公开(公告)号：US09177871B2

公开(公告)日：2015-11-03

申请号：US14143362

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。

公开(公告)号：US20140167119A1

公开(公告)日：2014-06-19

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L29/78 ,  H01L21/314

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US09177874B2

公开(公告)日：2015-11-03

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成光学平坦化层（OPL），在所述第一区域中的所述OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US20150064812A1

公开(公告)日：2015-03-05

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US09093526B2

公开(公告)日：2015-07-28

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L21/311 ,  H01L29/78 ,  H01L21/314 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US20140227869A1

公开(公告)日：2014-08-14

申请号：US14172135

申请日：2014-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。