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    Methods for fabricating integrated circuits with robust gate electrode structure protection
    1.
    发明授权
    Methods for fabricating integrated circuits with robust gate electrode structure protection 有权
    用于制造具有鲁棒栅极电极结构保护的集成电路的方法

    公开(公告)号：US09184260B2

    公开(公告)日：2015-11-10

    申请号：US14080558

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

    IPC: H01L21/425 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/165

    CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

    Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

    Gate silicidation
    2.
    发明授权
    Gate silicidation 有权
    栅极硅化

    公开(公告)号：US09034746B2

    公开(公告)日：2015-05-19

    申请号：US14524023

    申请日：2014-10-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/324 ,  H01L21/28

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅极的暴露的上部。

    GATE SILICIDATION
    3.
    发明申请
    GATE SILICIDATION 有权
    盖茨硅胶

    公开(公告)号：US20150044861A1

    公开(公告)日：2015-02-12

    申请号：US14524023

    申请日：2014-10-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L21/324 ,  H01L29/49 ,  H01L21/3205

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

    METHOD OF FORMING A SEMICONDUCTOR DEVICE EMPLOYING AN OPTICAL PLANARIZATION LAYER
    5.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE EMPLOYING AN OPTICAL PLANARIZATION LAYER 有权
    形成采用光学平面化层的半导体器件的方法

    公开(公告)号：US20150064812A1

    公开(公告)日：2015-03-05

    申请号：US14012563

    申请日：2013-08-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

    IPC: H01L21/311 ,  H01L21/66

    CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

    Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

    Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

    Gate silicidation
    6.
    发明授权
    Gate silicidation 有权
    栅极硅化

    公开(公告)号：US08906794B1

    公开(公告)日：2014-12-09

    申请号：US13956844

    申请日：2013-08-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

    IPC: H01L21/00 ,  H01L27/088 ,  H01L21/28

    CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

    Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION
    7.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION 有权
    用坚固的门电极结构保护制造集成电路的方法

    公开(公告)号：US20150132914A1

    公开(公告)日：2015-05-14

    申请号：US14080558

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

    Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
    8.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS 有权
    通过在预防或减少活动区域和/或分离区域的损失的同时进行湿酸蚀刻工艺来形成半导体器件的方法

    公开(公告)号：US20140227869A1

    公开(公告)日：2014-08-14

    申请号：US14172135

    申请日：2014-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

    Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

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