公开(公告)号：US10161915B2

公开(公告)日：2018-12-25

申请号：US14932372

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Remi Riviere ,  Arthur Hotzel

IPC: G01N29/46 ,  G01N29/24 ,  G03F1/62 ,  G03F1/84 ,  G01N29/11 ,  G01N29/34

Abstract: A method and apparatus for detecting changes in the vibrational mode spectra and/or elasticity of a pellicle without reliance upon visual inspection are provided. Embodiments include providing a pellicle, a lower surface of the pellicle attached to a photomask; directing light from a light source onto an upper surface of the pellicle at an angle to the upper surface; causing a deflection of the pellicle concurrently with the light being directed onto the pellicle; detecting light reflected off of the deflected pellicle; and characterizing a vibrational mode of the pellicle based on the detection.

公开(公告)号：US09177874B2

公开(公告)日：2015-11-03

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成光学平坦化层（OPL），在所述第一区域中的所述OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US20150064812A1

公开(公告)日：2015-03-05

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US09798244B2

公开(公告)日：2017-10-24

申请号：US14943086

申请日：2015-11-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arthur Hotzel ,  Philipp Jaschinsky ,  Remi Riviere ,  Wolfram Grundke

IPC: G03F1/50 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F7/70325 ,  G03F1/36 ,  G03F1/50 ,  G03F1/70

Abstract: Methods, apparatus, and system for minimizing defectivity in top-coat-free immersion photolithography are provided. Embodiments include forming a photomask by defining a first pattern including a main functional pattern in the photomask; and defining a second pattern including a sub-resolution fill pattern in the photomask in areas between or and/or within structures of the first pattern, the fill pattern having a pitch or range of pitches smaller than a minimum resolved pitch of the lithographic exposure and/or at least a part of the sub-resolution structures of the sub-resolution fill pattern not substantially modifying an imaging of any structure of the main functional pattern in the lithographic exposure.

公开(公告)号：US20160260607A1

公开(公告)日：2016-09-08

申请号：US14639620

申请日：2015-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Remi Riviere ,  Thomas Merelle

IPC: H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1108 ,  H01L21/0274 ,  H01L21/32139 ,  H01L27/1104

Abstract: A method includes providing a semiconductor structure and forming a plurality of gate structures over the semiconductor structure. The formation of the plurality of gate structures includes a first patterning process. The first patterning process includes a first photoresist exposure process and a second photoresist exposure process. In the first photoresist exposure process, a first photomask and a first illumination source pattern are used. The first photomask is adapted for providing a first gate cut photoresist pattern over a first area of the semiconductor structure. In the second photoresist exposure process, a second photomask and a second illumination source pattern that is different from the first illumination source pattern are used. The second photomask is adapted for providing a second gate cut photoresist pattern over a second area of the semiconductor structure.

Abstract translation: 一种方法包括提供半导体结构并在半导体结构上形成多个栅极结构。 多个栅极结构的形成包括第一图案化工艺。 第一图案化工艺包括第一光致抗蚀剂曝光工艺和第二光致抗蚀剂曝光工艺。 在第一光致抗蚀剂曝光工艺中，使用第一光掩模和第一照明源图案。 第一光掩模适于在半导体结构的第一区域上提供第一栅极切割光致抗蚀剂图案。 在第二光刻胶曝光处理中，使用不同于第一照明光源图案的第二光掩模和第二照明光源图案。 第二光掩模适于在半导体结构的第二区域上提供第二栅极切割光致抗蚀剂图案。