公开(公告)号：US20210050412A1

公开(公告)日：2021-02-18

申请号：US16538785

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Haiting Wang ,  Yong Jun Shi ,  Xiaoming Yang ,  Liu Jiang

IPC: H01L29/06 ,  H01L23/66 ,  H01L21/764 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

公开(公告)号：US20200350202A1

公开(公告)日：2020-11-05

申请号：US16400481

申请日：2019-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoming Yang ,  Haiting Wang ,  Hong Yu ,  Jeffrey Chee ,  Guoliang Zhu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033

Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

公开(公告)号：US10825811B2

公开(公告)日：2020-11-03

申请号：US16280343

申请日：2019-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoming Yang ,  Sipeng Gu ,  Jeffrey Chee ,  Keith H. Tabakman

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L21/02

Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

公开(公告)号：US20200266286A1

公开(公告)日：2020-08-20

申请号：US16280343

申请日：2019-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoming Yang ,  Sipeng Gu ,  Jeffrey Chee ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.