公开(公告)号：US20160225849A1

公开(公告)日：2016-08-04

申请号：US14613983

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Min-hwa CHI ,  Ashish BARASKAR ,  Jagar SINGH

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。

公开(公告)号：US20210050412A1

公开(公告)日：2021-02-18

申请号：US16538785

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Haiting Wang ,  Yong Jun Shi ,  Xiaoming Yang ,  Liu Jiang

IPC: H01L29/06 ,  H01L23/66 ,  H01L21/764 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

公开(公告)号：US20190229183A1

公开(公告)日：2019-07-25

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Hui ZANG ,  Chun Yu WONG ,  Kwan-Yong LIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US20190067474A1

公开(公告)日：2019-02-28

申请号：US15686257

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L29/10

Abstract: A polysilicon layer is deposited over the top surface of the source/drain region of a semiconductor fin in a vertical fin field effect transistor and recrystallized prior to the formation of an epitaxial source/drain region over the source/drain region. The recrystallized silicon material increases the area for deposition of the source/drain region, increasing the available contact area of the source/drain region and correspondingly decreasing the contact resistance thereto. Prior to recrystallization, the polysilicon layer may be made amorphous to improve the quality of the crystalline material for epitaxial growth.

公开(公告)号：US20190115426A1

公开(公告)日：2019-04-18

申请号：US15786284

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG ,  Xusheng WU

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US20170141031A1

公开(公告)日：2017-05-18

申请号：US15421698

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US20160284643A1

公开(公告)日：2016-09-29

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

Abstract translation: 提出了具有纳米线熔断体的半导体熔丝及其制造方法。 所述方法包括例如：制造半导体熔丝，所述半导体熔丝包括至少一个纳米线熔断体，所述制造包括：形成至少一个纳米线，所述至少一个纳米线包括半导体材料; 并且使所述至少一个纳米线与金属反应以形成所述半导体熔丝的所述至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。 在另一方面，提出了一种结构。 所述结构包括：半导体熔丝，所述半导体熔丝包括：至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。