公开(公告)号：US11585703B2

公开(公告)日：2023-02-21

申请号：US16700358

申请日：2019-12-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng-Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01K7/01 ,  G11C11/406 ,  G11C11/4072 ,  G11C7/04

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

公开(公告)号：US20210164845A1

公开(公告)日：2021-06-03

申请号：US16700358

申请日：2019-12-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01K7/01 ,  G11C11/406 ,  G11C7/04 ,  G11C11/4072

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

公开(公告)号：US20210043637A1

公开(公告)日：2021-02-11

申请号：US16532522

申请日：2019-08-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat Toh ,  Bin Liu ,  Shyue Seng Tan

IPC: H01L27/112 ,  H01L29/36 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L23/525 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.

公开(公告)号：US10797223B2

公开(公告)日：2020-10-06

申请号：US15882362

申请日：2018-01-29

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Yinjie Ding ,  Kangho Lee ,  Elgin Kiok Boone Quek

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L29/78 ,  H01L43/12

Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.

公开(公告)号：US10777734B2

公开(公告)日：2020-09-15

申请号：US16225005

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Samarth Agarwal ,  Ruchil Kumar Jain ,  Kiok Boone Elgin Quek

IPC: G11C11/00 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

公开(公告)号：US10724983B2

公开(公告)日：2020-07-28

申请号：US16215688

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Ming Tsang Tsai ,  Khee Yong Lim ,  Kiok Boone Elgin Quek

IPC: G01N27/414

Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.

公开(公告)号：US20200220530A1

公开(公告)日：2020-07-09

申请号：US16243433

申请日：2019-01-09

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh

IPC: H03K3/45 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.

公开(公告)号：US10374154B1

公开(公告)日：2019-08-06

申请号：US15874205

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES Singapore Pte Ltd

Inventor： Dimitri Houssameddine ,  Chenchen Jacob Wang ,  Bin Liu

IPC: H01L21/30 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

公开(公告)号：US20210135095A1

公开(公告)日：2021-05-06

申请号：US16671613

申请日：2019-11-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Ruchil Kumar Jain ,  Kiok Boone Elgin Quek

IPC: H01L43/06 ,  H01L43/14 ,  G01R33/00 ,  H01L27/22

Abstract: Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.

公开(公告)号：US20210013406A1

公开(公告)日：2021-01-14

申请号：US17038748

申请日：2020-09-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun Loy ,  Eng Huat Toh ,  Bin Liu ,  Shyue Seng Tan

IPC: H01L45/00 ,  H01L27/24

Abstract: Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.