公开(公告)号：US11087814B2

公开(公告)日：2021-08-10

申请号：US16508940

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob ,  Bipul C. Paul

IPC: G11C11/16

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US10997498B2

公开(公告)日：2021-05-04

申请号：US16366187

申请日：2019-03-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob

IPC: G11C16/28 ,  G06N3/063 ,  H01L27/24 ,  G11C16/24 ,  G11C16/08

Abstract: The present disclosure relates to a structure including a differential memory array circuit which is configured to perform a binary convolution of two input word operands by accumulating a summation of currents through a plurality of bits which are each arranged between a wordline and a sourceline in a horizontal direction and bitlines in a vertical direction.

公开(公告)号：US11776606B2

公开(公告)日：2023-10-03

申请号：US17365481

申请日：2021-07-01

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob ,  Bipul C. Paul

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1697

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US11056535B2

公开(公告)日：2021-07-06

申请号：US16425360

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01F10/32 ,  H01L45/00 ,  H01L43/02 ,  G11C13/00 ,  H01L27/24 ,  H01L23/528 ,  H01F41/32

Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating and using such structures. Non-volatile memory elements are arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal. A first field-effect transistor is coupled with the first terminal of the Wheatstone bridge arrangement, and a second field-effect transistor is coupled with the second terminal of the Wheatstone bridge arrangement.