公开(公告)号：US20230238428A1

公开(公告)日：2023-07-27

申请号：US17582550

申请日：2022-01-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rong-Ting Liou ,  Man Gu ,  Jeffrey B. Johnson ,  Wang Zheng ,  Jagar Singh ,  Haiting Wang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L29/7816 ,  H01L29/66681 ,  H01L21/76224

Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.

公开(公告)号：US10971625B2

公开(公告)日：2021-04-06

申请号：US16458178

申请日：2019-06-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Michael V Aquilino ,  Daniel Jaeger ,  Man Gu ,  Bradley Morgenfeld ,  Haiting Wang ,  Kavya Sree Duggimpudi ,  Wang Zheng

IPC: H01L29/08 ,  H01L27/112 ,  H01L29/78 ,  H01L21/822 ,  H01L29/66

Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

公开(公告)号：US11456384B2

公开(公告)日：2022-09-27

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

公开(公告)号：US20220005952A1

公开(公告)日：2022-01-06

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.

公开(公告)号：US20210351293A1

公开(公告)日：2021-11-11

申请号：US16870356

申请日：2020-05-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Rong-Ting Liou ,  Haiting Wang ,  Wenjun Li

IPC: H01L29/78 ,  H01L29/66

Abstract: A device is disclosed that includes a source region positioned in a first doped well region in a semiconductor substrate and a drain region positioned in a second doped well region in the substrate, wherein there is a well gap between the first doped well region and the second doped well region. The device also includes a gate structure that includes a first gate insulation layer positioned above an upper surface of the substrate, wherein the first gate insulation layer extends from a drain-side sidewall of the gate structure to a location above the well gap, and a second gate insulation layer having a first portion positioned above the upper surface of the substrate and a second portion positioned above the first gate insulation layer.

公开(公告)号：US11289474B2

公开(公告)日：2022-03-29

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Halting Wang ,  Tung-Hsing Lee

IPC: H01L21/00 ,  H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210327872A1

公开(公告)日：2021-10-21

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Haiting Wang ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.