公开(公告)号：US10903317B1

公开(公告)日：2021-01-26

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US09275911B2

公开(公告)日：2016-03-01

申请号：US13650591

申请日：2012-10-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。

公开(公告)号：US20240339538A1

公开(公告)日：2024-10-10

申请号：US18749813

申请日：2024-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US12094972B2

公开(公告)日：2024-09-17

申请号：US16406071

申请日：2019-05-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.