公开(公告)号：US20240068985A1

公开(公告)日：2024-02-29

申请号：US17821836

申请日：2022-08-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Laura J. Silverstein

IPC: G01N27/414 ,  B01L3/00 ,  G01N21/05

CPC classification number: G01N27/4145 ,  B01L3/502715 ,  G01N21/05 ,  B01L2300/047 ,  B01L2300/0636 ,  B01L2300/0645

Abstract: A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

公开(公告)号：US11107884B2

公开(公告)日：2021-08-31

申请号：US16538062

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Laura J. Silverstein ,  Cameron E. Luce

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

公开(公告)号：US11977258B1

公开(公告)日：2024-05-07

申请号：US18148029

申请日：2022-12-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Laura J. Silverstein ,  Steven M. Shank ,  Judson R. Holt ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/02 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/02042 ,  G02B6/02333 ,  G02B2006/121

Abstract: Disclosed are a structure with a substrate-embedded waveguide and a method of forming the structure. The waveguide includes cladding material lining a trench in a substrate, a core in the trench on the cladding material, and at least one cavity within the core. Each cavity extends from one end of the core toward the opposite end and contains a low refractive index material or is under vacuum so the waveguide is an arrow waveguide. An insulator layer is on the substrate and extends laterally over the waveguide and a semiconductor layer is on the insulator layer. Additionally, depending upon the embodiment, an additional waveguide can be aligned above the substrate-embedded waveguide either on the isolation region or on a waveguide extender that extends at least partially through the isolation region and the insulator layer to the waveguide.

公开(公告)号：US20230352570A1

公开(公告)日：2023-11-02

申请号：US17733118

申请日：2022-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Sarah A. McTaggart ,  Laura J. Silverstein ,  Qizhi Liu ,  Jason E. Stephens

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/732 ,  H01L29/66272 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/456

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.