公开(公告)号：US20220230955A1

公开(公告)日：2022-07-21

申请号：US17151346

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alamgir M. Arif ,  Sunil K. Singh ,  Dewei Xu ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

公开(公告)号：US11699650B2

公开(公告)日：2023-07-11

申请号：US17151346

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alamgir M. Arif ,  Sunil K. Singh ,  Dewei Xu ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L28/60

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

公开(公告)号：US11348867B2

公开(公告)日：2022-05-31

申请号：US17089775

申请日：2020-11-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

公开(公告)号：US20220139819A1

公开(公告)日：2022-05-05

申请号：US17089775

申请日：2020-11-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

公开(公告)号：US11107880B2

公开(公告)日：2021-08-31

申请号：US16408536

申请日：2019-05-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dewei Xu ,  Sunil K. Singh ,  Siva R. Dangeti ,  Seung-Yeop Kook

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/283 ,  H01L21/02

Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.