公开(公告)号：US20240429127A1

公开(公告)日：2024-12-26

申请号：US18340174

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dewei Xu ,  Ravi Prakash Srivastava ,  Zhuojie Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.

公开(公告)号：US20220230955A1

公开(公告)日：2022-07-21

申请号：US17151346

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alamgir M. Arif ,  Sunil K. Singh ,  Dewei Xu ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

公开(公告)号：US20220057445A1

公开(公告)日：2022-02-24

申请号：US17519742

申请日：2021-11-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US11699650B2

公开(公告)日：2023-07-11

申请号：US17151346

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alamgir M. Arif ,  Sunil K. Singh ,  Dewei Xu ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L28/60

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

公开(公告)号：US11215661B2

公开(公告)日：2022-01-04

申请号：US16872597

申请日：2020-05-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US20240243037A1

公开(公告)日：2024-07-18

申请号：US18154481

申请日：2023-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dewei Xu ,  Zhuojie Wu ,  Daniel Smith

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/528

Abstract: A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.

公开(公告)号：US20210356514A1

公开(公告)日：2021-11-18

申请号：US16872597

申请日：2020-05-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit incudes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US11693048B2

公开(公告)日：2023-07-04

申请号：US17519742

申请日：2021-11-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

CPC classification number: G01R31/2853

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US11348867B2

公开(公告)日：2022-05-31

申请号：US17089775

申请日：2020-11-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

公开(公告)号：US20220139819A1

公开(公告)日：2022-05-05

申请号：US17089775

申请日：2020-11-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dewei Xu ,  Sunil K. Singh ,  Seung-Yeop Kook ,  Roderick A. Augur

IPC: H01L23/522 ,  H01L49/02

Abstract: Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.